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authorArthur Heymans <arthur@aheymans.xyz>2021-10-27 20:58:32 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-10-29 00:52:29 +0000
commit05592ff1e63913f51b8c58e9e1e35c1ebca3f1a2 (patch)
treea5a079ffe215189e51cbd7e04fa71191b2e87eec /src/soc
parentb00bfd076502add705c894711b3b954a0d07d909 (diff)
soc/intel/icelake: select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
The Intel icelake rvp boards actually rely on this but this failure was hidden in a runtime error instead of a compile time error, due to weakly linked functions. Change-Id: Idbbe774efa1515ce1d34ce2ce8f87953300a3312 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58662 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/icelake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 5a825cbf54..0f0665bbb1 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
+ select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CNVI