diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 16:26:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 09:20:52 +0000 |
| commit | 05498a254d5364efb669f63aa4b042c91c123727 (patch) | |
| tree | 21fe95cd426c1da7a2ea54f44bfcb1566731308d /src/soc | |
| parent | e7f4beca19d538c47208b8a1b984cf0e39ff02b4 (diff) | |
src/soc: Get rid of whitespace before tab
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
29 files changed, 104 insertions, 104 deletions
diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index 4bf456ab0e..a75a440f8d 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -363,7 +363,7 @@ AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) ConcatenateNodes(AllocNodePtr, NextNodePtr); } else { /*AllocNodePtr->NextNodeOffset = - * FreedNodePtr->NextNodeOffset; */ + * FreedNodePtr->NextNodeOffset; */ AllocNodePtr->NextNodeOffset = NextNodeOffset; } /* diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index 9f0019d4dd..cfbaaa71a3 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -84,7 +84,7 @@ endif # CustomerRevisionID; /* Customer Revision ID */ # # SBIUsage /* Boot Image Usage */ -# NONE 0 /* All purposes */ +# NONE 0 /* All purposes */ # SLEEP 1 # DEEP_SLEEP 2 # EXCEPTION 4 diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index c2084576c1..ff5dc87f78 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -1638,7 +1638,7 @@ wakeup: asm( "movw r3, #0x4c64\n" "movt r3, #0x0302\n" - "ldr r5, [r3]\n" + "ldr r5, [r3]\n" "mov lr, #0\n" "mov pc, r5\n"); #endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */ diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S index 92289a0145..fbf2d31dc3 100644 --- a/src/soc/intel/apollolake/exit_car_fsp.S +++ b/src/soc/intel/apollolake/exit_car_fsp.S @@ -28,11 +28,11 @@ * caching settings are based on an 8MiB Flash Size given as a * parameter to TempRamInit. * - * TempRamExit MTRR Settings: - * 0x00000000 - 0x0009FFFF | Write Back - * 0x000C0000 - Top of Low Memory | Write Back - * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect - * 0x100000000 - Top of High Memory | Write Back + * TempRamExit MTRR Settings: + * 0x00000000 - 0x0009FFFF | Write Back + * 0x000C0000 - Top of Low Memory | Write Back + * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect + * 0x100000000 - Top of High Memory | Write Back */ .text diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 580c4eb80b..93e80cbab2 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -58,8 +58,8 @@ #define GPSSUS_COUNT 44 /* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 +#define GPIO_USE_MMIO 0 +#define GPIO_USE_LEGACY 1 #define GPIO_DIR_OUTPUT 0 #define GPIO_DIR_INPUT 1 @@ -317,12 +317,12 @@ { .pad_conf0 = GPIO_LIST_END } /* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT GPIO_INPUT_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU #define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K +#define GPIO_INPUT_PD GPIO_INPUT_PD_20K #define GPIO_NC GPIO_OUT_HIGH -#define GPIO_DEFAULT GPIO_FUNC0 +#define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */ #define GPIO_MAX_DIRQS 16 diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e735f0116c..689d4d55cc 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -20,10 +20,10 @@ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define SINGLE_PCTL (1 << 11) +#define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 -#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) -#define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc diff --git a/src/soc/intel/baytrail/include/soc/xhci.h b/src/soc/intel/baytrail/include/soc/xhci.h index ec643c1725..d509b51a6a 100644 --- a/src/soc/intel/baytrail/include/soc/xhci.h +++ b/src/soc/intel/baytrail/include/soc/xhci.h @@ -33,7 +33,7 @@ # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c index 61e95fabc9..e1e7542ed8 100644 --- a/src/soc/intel/baytrail/romstage/early_spi.c +++ b/src/soc/intel/baytrail/romstage/early_spi.c @@ -22,7 +22,7 @@ #include <soc/romstage.h> #include <soc/spi.h> -#define SPI_CYCLE_DELAY 10 /* 10us */ +#define SPI_CYCLE_DELAY 10 /* 10us */ #define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ #define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl index 76804f8b8a..ef0eaba476 100644 --- a/src/soc/intel/broadwell/acpi/pch.asl +++ b/src/soc/intel/broadwell/acpi/pch.asl @@ -31,7 +31,7 @@ Scope (\) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select + HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable } diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/acpi/pci_irqs.asl index 6565334fdf..44263ea6ab 100644 --- a/src/soc/intel/broadwell/acpi/pci_irqs.asl +++ b/src/soc/intel/broadwell/acpi/pci_irqs.asl @@ -29,11 +29,11 @@ Method(_PRT) Package() { 0x001cffff, 1, 0, 17 }, Package() { 0x001cffff, 2, 0, 18 }, Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 + // EHCI 0:1d.0 Package() { 0x001dffff, 0, 0, 19 }, // Audio DSP (Smart Sound) 0:13.0 Package() { 0x0013ffff, 0, 0, 23 }, - // XHCI 0:14.0 + // XHCI 0:14.0 Package() { 0x0014ffff, 0, 0, 18 }, // LPC devices 0:1f.0 Package() { 0x001fffff, 0, 0, 22 }, @@ -61,11 +61,11 @@ Method(_PRT) Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 + // EHCI 0:1d.0 Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, // Audio DSP (Smart Sound) 0:13.0 Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - // XHCI 0:14.0 + // XHCI 0:14.0 Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, // LPC device 0:1f.0 Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index b794ede967..90cd3701b5 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -39,7 +39,7 @@ #define SUS_PWR_FLR (1 << 16) #define PME_B0_S5_DIS (1 << 15) #define PWR_FLR (1 << 14) -#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) +#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13) #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) #define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10) #define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10) diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 512fbbe0f3..26f0a632a0 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -69,7 +69,7 @@ static int send_heci_reset_message(void) reply_size = sizeof(reply); memset(&reply, 0, reply_size); if (!heci_receive(&reply, &reply_size)) - return -1; + return -1; if (reply.result != MKHI_STATUS_SUCCESS) { printk(BIOS_DEBUG, "Returned Mkhi Status is not success!\n"); return -1; diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 02aeefe9ab..684f82786a 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -94,7 +94,7 @@ clear_var_mtrr: * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing */ - movl $0x80000008, %eax /* Address sizes leaf */ + movl $0x80000008, %eax /* Address sizes leaf */ cpuid sub $32, %al movzx %al, %eax @@ -193,7 +193,7 @@ car_init_done: movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax - pushl %eax /* tsc[31:0] */ + pushl %eax /* tsc[31:0] */ before_carstage: post_code(0x2A) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index a389e34154..2ae56dfa7b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -22,7 +22,7 @@ #define SPIBAR_BIOS_CONTROL 0xdc /* Bit definitions for BIOS_CONTROL */ -#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) +#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1) #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) @@ -113,21 +113,21 @@ #define SPIBAR_FPR_MAX 5 /* Programmable values for OPMENU_LOWER(0xA8) & OPMENU_UPPER(0xAC) register */ -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ #define SPI_OPTYPE_7 0x02 /* Read, address required */ #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index 66eaddf5eb..811d27354e 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -57,7 +57,7 @@ static void sd_fill_ssdt(struct device *dev) static struct device_operations dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, + .enable_resources = &pci_dev_enable_resources, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = &sd_fill_ssdt, #endif diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index 262ac55cba..3167c183d8 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -177,7 +177,7 @@ Device (LPCB) Name(BUF0,ResourceTemplate() { IO(Decode16,0x02F8,0x02F8,0x01,0x08) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17} + Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {17} }) Return(BUF0) } diff --git a/src/soc/intel/denverton_ns/exit_car_fsp.S b/src/soc/intel/denverton_ns/exit_car_fsp.S index 2ec625b4d2..83d5a330e7 100644 --- a/src/soc/intel/denverton_ns/exit_car_fsp.S +++ b/src/soc/intel/denverton_ns/exit_car_fsp.S @@ -29,11 +29,11 @@ * caching settings are based on an 8MiB Flash Size given as a * parameter to TempRamInit. * - * TempRamExit MTRR Settings: - * 0x00000000 - 0x0009FFFF | Write Back - * 0x000C0000 - Top of Low Memory | Write Back - * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect - * 0x100000000 - Top of High Memory | Write Back + * TempRamExit MTRR Settings: + * 0x00000000 - 0x0009FFFF | Write Back + * 0x000C0000 - Top of Low Memory | Write Back + * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect + * 0x100000000 - Top of High Memory | Write Back */ .text diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 7c81151b51..767755454b 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -56,8 +56,8 @@ #define GPSSUS_COUNT 44 /* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 +#define GPIO_USE_MMIO 0 +#define GPIO_USE_LEGACY 1 #define GPIO_DIR_OUTPUT 0 #define GPIO_DIR_INPUT 1 @@ -291,12 +291,12 @@ { .pad_conf0 = GPIO_LIST_END } /* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT GPIO_INPUT_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU #define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K +#define GPIO_INPUT_PD GPIO_INPUT_PD_20K #define GPIO_NC GPIO_INPUT_PU_20K -#define GPIO_DEFAULT GPIO_FUNC0 +#define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */ #define GPIO_MAX_DIRQS 16 diff --git a/src/soc/intel/fsp_baytrail/include/soc/xhci.h b/src/soc/intel/fsp_baytrail/include/soc/xhci.h index ec643c1725..d509b51a6a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/xhci.h +++ b/src/soc/intel/fsp_baytrail/include/soc/xhci.h @@ -33,7 +33,7 @@ # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 1abe9cb884..600be27957 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -25,7 +25,7 @@ #include <string.h> #define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) +#define PCR_DMI_GCS_BILD (1 << 0) static void lpc_lockdown_config(const struct soc_intel_skylake_config *config) { @@ -56,9 +56,9 @@ static void dmi_lockdown_config(void) * When set, prevents GCS.BBS from being changed * GCS.BBS: (Boot BIOS Strap) This field determines the destination * of accesses to the BIOS memory range. - * Bits Description - * "0b": SPI - * "1b": LPC/eSPI + * Bits Description + * "0b": SPI + * "1b": LPC/eSPI */ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); } diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h index bfeebae2dc..9af4b20e2f 100644 --- a/src/soc/nvidia/tegra/types.h +++ b/src/soc/nvidia/tegra/types.h @@ -18,7 +18,7 @@ #define EFAULT 1 #define EINVAL 2 -#define ETIMEDOUT 3 +#define ETIMEDOUT 3 #define ENOSPC 4 #define ENOSYS 5 #define EPTR 6 diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 8d5a264ff7..e66cbbd9dc 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -216,7 +216,7 @@ void display_startup(struct device *dev) { struct soc_nvidia_tegra124_config *config = dev->chip_info; struct display_controller *disp_ctrl = (void *)config->display_controller; - struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE; + struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE; struct tegra_dc *dc = &dc_data; u32 plld_rate; diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index 36888b132c..7cac4ba319 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -471,12 +471,12 @@ enum { #define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ -#define HCLK_DISABLE (1 << 7) -#define HCLK_DIVISOR_SHIFT 4 -#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) -#define PCLK_DISABLE (1 << 3) -#define PCLK_DIVISOR_SHIFT 0 -#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define HCLK_DISABLE (1 << 7) +#define HCLK_DIVISOR_SHIFT 4 +#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define PCLK_DISABLE (1 << 3) +#define PCLK_DIVISOR_SHIFT 0 +#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index c5ad0c76a5..d9137adfe4 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -606,8 +606,8 @@ static void dump_sor_reg(struct tegra_dc_sor_data *sor) static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor, int is_lvds) { - const struct tegra_dc *dc = sor->dc; - const struct tegra_dc_dp_data *dp = dc->out; + const struct tegra_dc *dc = sor->dc; + const struct tegra_dc_dp_data *dp = dc->out; const struct tegra_dc_dp_link_config *link_cfg = &dp->link_cfg; const struct soc_nvidia_tegra124_config *config = dc->config; diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 781a4e2482..652bcaaf27 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -416,7 +416,7 @@ enum { #define PLLM_MISC2_KCP_SHIFT 1 #define PLLM_MISC2_KVCO_SHIFT 0 #define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) -#define PLLM_EN_LCKDET (1 << 4) +#define PLLM_EN_LCKDET (1 << 4) /* PLLU specific registers */ #define PLLU_MISC_IDDQ (1U << 31) @@ -527,12 +527,12 @@ enum { #define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ -#define HCLK_DISABLE (1 << 7) -#define HCLK_DIVISOR_SHIFT 4 -#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) -#define PCLK_DISABLE (1 << 3) -#define PCLK_DIVISOR_SHIFT 0 -#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define HCLK_DISABLE (1 << 7) +#define HCLK_DIVISOR_SHIFT 4 +#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define PCLK_DISABLE (1 << 3) +#define PCLK_DIVISOR_SHIFT 0 +#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) /* CPU_SOFTRST_CTRL2_0 0x388 */ #define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h index 4b4f14e01d..dbaaa2233c 100644 --- a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h +++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h @@ -149,7 +149,7 @@ #define PKT_LP (1 << 30) #define NUM_PKT_SEQ 12 -#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20) +#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20) #define DSIB_MODE_SHIFT 1 #define DSIB_MODE_CSI (0 << DSIB_MODE_SHIFT) #define DSIB_MODE_DSI (1 << DSIB_MODE_SHIFT) diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index 4a3aa49140..18751a8753 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -101,12 +101,12 @@ #define USB_HOST1_PHY_BASE 0x110F8800 #define GSBI_4 4 -#define UART1_DM_BASE 0x12450000 -#define UART_GSBI1_BASE 0x12440000 +#define UART1_DM_BASE 0x12450000 +#define UART_GSBI1_BASE 0x12440000 #define UART2_DM_BASE 0x12490000 #define UART_GSBI2_BASE 0x12480000 -#define UART4_DM_BASE 0x16340000 -#define UART_GSBI4_BASE 0x16300000 +#define UART4_DM_BASE 0x16340000 +#define UART_GSBI4_BASE 0x16300000 #define UART2_DM_BASE 0x12490000 #define UART_GSBI2_BASE 0x12480000 @@ -135,25 +135,25 @@ #define GSBI_QUP6_BASE (GSBI6_BASE + 0x80000) #define GSBI_QUP7_BASE (GSBI7_BASE + 0x80000) -#define GSBI_CTL_PROTO_I2C 2 -#define GSBI_CTL_PROTO_CODE_SFT 4 -#define GSBI_CTL_PROTO_CODE_MSK 0x7 -#define GSBI_HCLK_CTL_GATE_ENA 6 -#define GSBI_HCLK_CTL_BRANCH_ENA 4 -#define GSBI_QUP_APPS_M_SHFT 16 -#define GSBI_QUP_APPS_M_MASK 0xFF -#define GSBI_QUP_APPS_D_SHFT 0 -#define GSBI_QUP_APPS_D_MASK 0xFF -#define GSBI_QUP_APPS_N_SHFT 16 -#define GSBI_QUP_APPS_N_MASK 0xFF -#define GSBI_QUP_APPS_ROOT_ENA_SFT 11 -#define GSBI_QUP_APPS_BRANCH_ENA_SFT 9 -#define GSBI_QUP_APPS_MNCTR_EN_SFT 8 -#define GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3 -#define GSBI_QUP_APPS_MNCTR_MODE_SFT 5 -#define GSBI_QUP_APPS_PRE_DIV_MSK 0x3 -#define GSBI_QUP_APPS_PRE_DIV_SFT 3 -#define GSBI_QUP_APPS_SRC_SEL_MSK 0x7 +#define GSBI_CTL_PROTO_I2C 2 +#define GSBI_CTL_PROTO_CODE_SFT 4 +#define GSBI_CTL_PROTO_CODE_MSK 0x7 +#define GSBI_HCLK_CTL_GATE_ENA 6 +#define GSBI_HCLK_CTL_BRANCH_ENA 4 +#define GSBI_QUP_APPS_M_SHFT 16 +#define GSBI_QUP_APPS_M_MASK 0xFF +#define GSBI_QUP_APPS_D_SHFT 0 +#define GSBI_QUP_APPS_D_MASK 0xFF +#define GSBI_QUP_APPS_N_SHFT 16 +#define GSBI_QUP_APPS_N_MASK 0xFF +#define GSBI_QUP_APPS_ROOT_ENA_SFT 11 +#define GSBI_QUP_APPS_BRANCH_ENA_SFT 9 +#define GSBI_QUP_APPS_MNCTR_EN_SFT 8 +#define GSBI_QUP_APPS_MNCTR_MODE_MSK 0x3 +#define GSBI_QUP_APPS_MNCTR_MODE_SFT 5 +#define GSBI_QUP_APPS_PRE_DIV_MSK 0x3 +#define GSBI_QUP_APPS_PRE_DIV_SFT 3 +#define GSBI_QUP_APPS_SRC_SEL_MSK 0x7 #define GSBI_QUP_APSS_MD_REG(gsbi_n) ((MSM_CLK_CTL_BASE + 0x29c8) + \ diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index a8d991059f..f8f4e4da93 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -123,7 +123,7 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) write32(&dwc3->uctl, 0x32 << 22 | /* (default) reference clock period in ns */ 0x1 << 15 | /* (default) XHCI compliant device addressing */ - 0x10 << 0); /* (default) devices time out after 32us */ + 0x10 << 0); /* (default) devices time out after 32us */ udelay(5); @@ -149,7 +149,7 @@ static void setup_phy(struct usb_qc_phy *phy) 0x1 << 18 | /* use ref clock from core */ 0x1 << 17 | /* (default) unclamp DPSE VLS */ 0x1 << 11 | /* force xo/bias/pll to stay on in suspend */ - 0x1 << 9 | /* (default) unclamp IDHV */ + 0x1 << 9 | /* (default) unclamp IDHV */ 0x1 << 8 | /* (default) unclamp VLS (again???) */ 0x1 << 7 | /* (default) unclamp HV VLS */ 0x7 << 4 | /* select frequency (no idea which one) */ diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index 457c51dd1e..f304d8fcd0 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -233,7 +233,7 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8); #define THS_PRE_PROGRAM_EN BIT(7) #define THS_ZERO_PROGRAM_EN BIT(6) -#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 +#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 #define PLL_LPF_AND_CP_CONTROL 0x12 #define PLL_INPUT_DIVIDER_RATIO 0x17 |