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authorFelix Held <felix-coreboot@felixheld.de>2023-12-14 18:52:40 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-12-16 00:41:25 +0000
commitf0c67127a90862de46625880e0d05b3c63081359 (patch)
tree141a587e86b00f6df5a1ec0b0a9f1fc5828571b3 /src/soc
parent7f19d205944d46483bf414420118b8d937a113ce (diff)
soc/amd/genoa/fch: add fch_init_acpi_ports
Make sure that the APMC SMI command IO port is configured to what coreboot expects and enable the SMI generation for the APMC SMI command port. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4fc259dea125a16556a01b80a3d5e6fb476044a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79531 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/genoa/fch.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/fch.c b/src/soc/amd/genoa/fch.c
index f93408714b..c9779571da 100644
--- a/src/soc/amd/genoa/fch.c
+++ b/src/soc/amd/genoa/fch.c
@@ -74,9 +74,17 @@ static void set_pci_irqs(void)
/* TODO: PIRQ configuration */
}
+static void fch_init_acpi_ports(void)
+{
+ /* Configure and enable APMC SMI Command Port */
+ pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
+ configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+}
+
static void fch_init(void *unused)
{
set_pci_irqs();
+ fch_init_acpi_ports();
}
/*