summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2020-02-20 19:41:17 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-02-24 12:56:03 +0000
commitef90609cbb4229ccc242f67c48a8e14273bf0aac (patch)
treebb1ce9a66ee7a0d0458365f284f15a028689816b /src/soc
parent183ad06f522b279328acb70dfba52d31f9ff9c91 (diff)
src: capitalize 'RAM'
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/glk_page_map.txt2
-rw-r--r--src/soc/intel/denverton_ns/Kconfig2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt
index e96a2db0ea..1a5f11fc0a 100644
--- a/src/soc/intel/apollolake/glk_page_map.txt
+++ b/src/soc/intel/apollolake/glk_page_map.txt
@@ -1,7 +1,7 @@
0x00000000, 0x100000000, WB, # RAM
# Above entry is needed because below 4G allocated memory range is
# only known after FSP memory init completes. However, FSP migrates to memory
-# from cache as ram before it exits FSP Memory Init. Hence we need to add
+# from cache as RAM before it exits FSP Memory Init. Hence we need to add
# page table entries for this entire range before FSP Memory Init. The
# overlapped MMIO ranges will be overridden by below entries.
0xd0000000, 0x100000000, UC, NX # All of MMIO
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index aed2beb3fd..9a611271ab 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -59,7 +59,7 @@ config MMCONF_BASE_ADDRESS
default 0xe0000000
config FSP_T_ADDR
- hex "Intel FSP-T (temp ram init) binary location"
+ hex "Intel FSP-T (temp RAM init) binary location"
depends on ADD_FSP_BINARIES && FSP_CAR
default 0xfff30000
help