From ef90609cbb4229ccc242f67c48a8e14273bf0aac Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 20 Feb 2020 19:41:17 +0100 Subject: src: capitalize 'RAM' Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/glk_page_map.txt | 2 +- src/soc/intel/denverton_ns/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc') diff --git a/src/soc/intel/apollolake/glk_page_map.txt b/src/soc/intel/apollolake/glk_page_map.txt index e96a2db0ea..1a5f11fc0a 100644 --- a/src/soc/intel/apollolake/glk_page_map.txt +++ b/src/soc/intel/apollolake/glk_page_map.txt @@ -1,7 +1,7 @@ 0x00000000, 0x100000000, WB, # RAM # Above entry is needed because below 4G allocated memory range is # only known after FSP memory init completes. However, FSP migrates to memory -# from cache as ram before it exits FSP Memory Init. Hence we need to add +# from cache as RAM before it exits FSP Memory Init. Hence we need to add # page table entries for this entire range before FSP Memory Init. The # overlapped MMIO ranges will be overridden by below entries. 0xd0000000, 0x100000000, UC, NX # All of MMIO diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index aed2beb3fd..9a611271ab 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -59,7 +59,7 @@ config MMCONF_BASE_ADDRESS default 0xe0000000 config FSP_T_ADDR - hex "Intel FSP-T (temp ram init) binary location" + hex "Intel FSP-T (temp RAM init) binary location" depends on ADD_FSP_BINARIES && FSP_CAR default 0xfff30000 help -- cgit v1.2.3