diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-07-31 20:23:41 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-11 08:31:43 +0000 |
| commit | 9394bace4e798197414bc8e05be0bcbc0a767fe7 (patch) | |
| tree | 4e19e2e9e4a1b682c186aaa2d64d893c69e2a213 /src/soc | |
| parent | 12abfb43dc0a9cbabdb60f04254fff04bf14a8ce (diff) | |
soc/intel/cnvi: Add CWAR Fields
These fields are used to monitor events on CNVi.
Intel document #559910 details this.
Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/cnvi/cnvi.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 4c434b2260..609c473341 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -68,6 +68,24 @@ static void cnvw_fill_ssdt(const struct device *dev) acpigen_write_field("CWAR", fields, ARRAY_SIZE(fields), FIELD_WORDACC | FIELD_NOLOCK | FIELD_PRESERVE); +/* + * Field (CWAR, ByteAcc, NoLock, Preserve) + * { + * Offset (0xcd), + * PMEE, 1, + * , 6, + * PMES, 1 + * } + */ + struct fieldlist fields2[] = { + FIELDLIST_OFFSET(0xcd), + FIELDLIST_NAMESTR("PMEE", 1), + FIELDLIST_RESERVED(6), + FIELDLIST_NAMESTR("PMES", 1), + }; + acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2), + FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); + acpigen_write_scope_end(); } |