From 9394bace4e798197414bc8e05be0bcbc0a767fe7 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Wed, 31 Jul 2024 20:23:41 +0100 Subject: soc/intel/cnvi: Add CWAR Fields These fields are used to monitor events on CNVi. Intel document #559910 details this. Change-Id: I3c1efc039e929ad1eeb8a0dd7c176e370e502e0c Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/83709 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Nicholas Sudsgaard --- src/soc/intel/common/block/cnvi/cnvi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/soc') diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 4c434b2260..609c473341 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -68,6 +68,24 @@ static void cnvw_fill_ssdt(const struct device *dev) acpigen_write_field("CWAR", fields, ARRAY_SIZE(fields), FIELD_WORDACC | FIELD_NOLOCK | FIELD_PRESERVE); +/* + * Field (CWAR, ByteAcc, NoLock, Preserve) + * { + * Offset (0xcd), + * PMEE, 1, + * , 6, + * PMES, 1 + * } + */ + struct fieldlist fields2[] = { + FIELDLIST_OFFSET(0xcd), + FIELDLIST_NAMESTR("PMEE", 1), + FIELDLIST_RESERVED(6), + FIELDLIST_NAMESTR("PMES", 1), + }; + acpigen_write_field("CWAR", fields2, ARRAY_SIZE(fields2), + FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); + acpigen_write_scope_end(); } -- cgit v1.2.3