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| author | Raul E Rangel <rrangel@chromium.org> | 2021-05-04 15:42:09 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-09 18:09:53 +0000 |
| commit | fd7ed87746d763feff7d26dba9598b505e8750c1 (patch) | |
| tree | 49e79ef6e693f47daca4ea3355711db328a6a15b /src/soc/ucb | |
| parent | 7b84b02492ec3ae1209c369f9149dd12e69d158a (diff) | |
soc/amd/cezanne: Populate PCI_INTR registers
This uses the new FSP PCI methods to pull the routing table and populate
the pirq data structure.
BUG=b:184766519
TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/ucb')
0 files changed, 0 insertions, 0 deletions