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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-06-01 14:50:07 +0200 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-05-26 08:25:50 +0000 |
commit | fbc508fbb84ddbd047a8fde271c3877f032e48d1 (patch) | |
tree | b36ccbc56e9d62a4ff28b076b0611c815ad0d95d /src/soc/ucb | |
parent | e3011451cccece7668f95e59dfb6f61c878b7e0a (diff) |
mb/intel/dg41wv: Add mainboard
This board was used a test target for the x4x DDR3 raminit patches and
has an easy to access DIP8 socket.
What is tested and works:
* S3 resume
* PEG, PCI, USB, SATA
* Sound
* Ethernet
* Native graphic init (textmode and linear fb) on the VGA output
* Passing memtest86+ with 2 2Rx8 4G dimms
* PS2 Keyboard
* Flashing coreboot internally from vendor BIOS.
What does not work:
* Running dram at 533 MHz (limited at 400MHz currently)
Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux
4.10.
Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/ucb')
0 files changed, 0 insertions, 0 deletions