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authorPhilipp Hug <philipp@hug.cx>2019-09-04 09:24:45 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-12-06 15:09:48 +0000
commit934ae21b52492c9c730dc5accd2900b32c5c1492 (patch)
treee8fecc91580592ac857326077ce9c486e31af017 /src/soc/ucb
parent8cb5ea7879cf82b79ab9a2c4342c542a167943bf (diff)
mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
TEST=Set MAX_CPUS=2 and run qemu with -smp 2 Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
Diffstat (limited to 'src/soc/ucb')
-rw-r--r--src/soc/ucb/riscv/Makefile.inc4
-rw-r--r--src/soc/ucb/riscv/ipi.c21
2 files changed, 0 insertions, 25 deletions
diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc
index ef03642d89..80899d570f 100644
--- a/src/soc/ucb/riscv/Makefile.inc
+++ b/src/soc/ucb/riscv/Makefile.inc
@@ -1,11 +1,7 @@
ifeq ($(CONFIG_SOC_UCB_RISCV),y)
-bootblock-y += ipi.c
-
romstage-y += cbmem.c
-romstage-y += ipi.c
ramstage-y += cbmem.c
-ramstage-y += ipi.c
endif
diff --git a/src/soc/ucb/riscv/ipi.c b/src/soc/ucb/riscv/ipi.c
deleted file mode 100644
index 80307a8d2a..0000000000
--- a/src/soc/ucb/riscv/ipi.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 HardenedLinux
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <mcall.h>
-
-/* TODO: Please implement this function */
-void set_msip(int hartid, int val)
-{
-}