From 934ae21b52492c9c730dc5accd2900b32c5c1492 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Wed, 4 Sep 2019 09:24:45 -0700 Subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. TEST=Set MAX_CPUS=2 and run qemu with -smp 2 Signed-off-by: Philipp Hug Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246 Tested-by: build bot (Jenkins) Reviewed-by: Xiang Wang --- src/soc/ucb/riscv/Makefile.inc | 4 ---- src/soc/ucb/riscv/ipi.c | 21 --------------------- 2 files changed, 25 deletions(-) delete mode 100644 src/soc/ucb/riscv/ipi.c (limited to 'src/soc/ucb') diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index ef03642d89..80899d570f 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,11 +1,7 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) -bootblock-y += ipi.c - romstage-y += cbmem.c -romstage-y += ipi.c ramstage-y += cbmem.c -ramstage-y += ipi.c endif diff --git a/src/soc/ucb/riscv/ipi.c b/src/soc/ucb/riscv/ipi.c deleted file mode 100644 index 80307a8d2a..0000000000 --- a/src/soc/ucb/riscv/ipi.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -/* TODO: Please implement this function */ -void set_msip(int hartid, int val) -{ -} -- cgit v1.2.3