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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-16 00:30:15 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-17 15:45:57 +0000 |
| commit | 7a92e3895f84daab1c9051eede1d8a33446321a5 (patch) | |
| tree | 3ea9f47ce084c2c4669f3c03ef3f506e62f5fffb /src/soc/ucb/riscv | |
| parent | 35f0a8fec7cd6127838fbe5a36170ba73efa49a4 (diff) | |
soc/amd/picasso/agesa_acpi: add cast before right shift
Without the cast the left shift is done on a 32 bit variable that gets
extended to 64 bits afterwards which results in missing MSBs. To avoid
this, do the cast to 64 bits before the left shift.
Found-by: Coverity CID 1443793, 1443794
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/ucb/riscv')
0 files changed, 0 insertions, 0 deletions