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authorFelix Held <felix-coreboot@felixheld.de>2022-02-07 21:11:25 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-11 14:18:54 +0000
commit6ba6bc24eb58c77f38a0818dd05da865abfb659b (patch)
treeb329fc6bea27644225591a691a659ab680978668 /src/soc/ti/am335x
parentcdbfa6e63788a7c71e3167378657d0afb8beab53 (diff)
soc/amd/common/block/lpc/espi_util: add decode range register helpers
Introduce and use functions to translate eSPI IO/MMIO decode range IDs into the corresponding register bits and the IO/MMIO range and size register IDs into register offsets. This is a preparation to support the additional eSPI decode ranges on Sabrina where not all enable bits and base/size registers for one type of decode ranges are consecutive. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/ti/am335x')
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