soc/ti/am335x: Enable MMU in bootblock

Enables the MMU primarily to allow the unaligned word reads that the
FMAP code requires. Without enabling this, the chip gets data access
exceptions.

Enabling the MMU also gives some advantages in allowing the icache and
dcache to be enabled, so is probably worth doing regardless.

Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 17 insertions, 5 deletions

diff --git a/src/soc/ti/am335x/bootblock.c b/src/soc/ti/am335x/bootblock.c
index 985e1a1a0b..11bc4593e1 100644
--- a/src/soc/ti/am335x/bootblock.c
+++ b/src/soc/ti/am335x/bootblock.c
@@ -4,13 +4,25 @@
 
 #include <arch/cache.h>
 #include <bootblock_common.h>
+#include <symbols.h>
+
+#define SRAM_START          ((uintptr_t)_sram / MiB)
+#define SRAM_END            (DIV_ROUND_UP((uintptr_t)_esram, MiB))
+
+#define DRAM_START          ((uintptr_t)_dram / MiB)
+#define DRAM_SIZE           (CONFIG_DRAM_SIZE_MB)
 
 void bootblock_soc_init(void)
 {
-	uint32_t sctlr;
+	mmu_init();
+
+	/* Map everything strongly ordered by default */
+	mmu_config_range(0, 4096, DCACHE_OFF);
+
+	mmu_config_range(SRAM_START, SRAM_END - SRAM_START,
+		DCACHE_WRITEBACK);
+
+	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
 
-	/* enable dcache */
-	sctlr = read_sctlr();
-	sctlr |= SCTLR_C;
-	write_sctlr(sctlr);
+	dcache_mmu_enable();
 }