diff options
| author | Annie Chen <Chen.AnnieET@inventec.com> | 2023-06-02 09:57:28 +0800 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-07-20 10:11:07 +0000 |
| commit | d31cbc74d1317aa5beb8619d93b9337d2c1370de (patch) | |
| tree | 962bc7a3fd0aeec838e69186c70e0e1bc45c967d /src/soc/sifive | |
| parent | 77b71cf9d7e63e522b801323648681f64165ae40 (diff) | |
mb/inventec: Add Intel SPR server board Inventec Transformers
CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector
BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC
Test:
The board boots to Linux 4.19.6 with all 192 cores available.
Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com>
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/sifive')
0 files changed, 0 insertions, 0 deletions