summaryrefslogtreecommitdiff
path: root/src/soc/sifive
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2023-11-16 16:06:49 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-12-19 13:11:43 +0000
commit7b9c6472179dc7a688c7728e4371d0cde0e7791a (patch)
tree672261aaacdb84e08822caaf6a17548b72867f75 /src/soc/sifive
parent83e9f048024ab3a527d886d4591b29513c628f79 (diff)
nb/amd/pi/00730F01: assign northbridge ops in chipset devicetree
Since the northbridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the northbridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7faaa468ff77e05c378c5555622c3584cfe3f81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/sifive')
0 files changed, 0 insertions, 0 deletions