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| author | Ronald G Minnich <rminnich@gmail.com> | 2024-03-15 21:56:20 -0700 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2024-03-22 23:01:48 +0000 |
| commit | 200f7b7ee13b98d726bd0e5de2792a14c558a7ea (patch) | |
| tree | 3df0dfd97c06196af2a2d92aef7e88912f088e4b /src/soc/sifive/fu540 | |
| parent | 87fa1d07b57a8087da031e3db72695f0547db0c9 (diff) | |
arch/riscv: add Kconfig variable RISCV_SOC_HAS_MENVCFG
Older parts do not have the menvcfg csr.
Provide a Kconfig variable, default y, to enable it.
Check the variable in the payload code, when coreboot SBI
is used, and print out if it is enabled.
The SiFive FU540 and FU740 do not support this register;
set the variable to n for those parts.
Add constants for this new CSR.
Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/sifive/fu540')
| -rw-r--r-- | src/soc/sifive/fu540/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 97931fd09c..fb15762204 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -48,4 +48,9 @@ config OPENSBI_PLATFORM config OPENSBI_TEXT_START hex default 0x80000000 + +config RISCV_SOC_HAS_MENVCFG + bool + default n + endif |