diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2023-10-04 17:42:37 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-10-20 19:31:13 +0000 |
| commit | 244e3ffcbc84ce7f5139771fd6419ebcdab6255c (patch) | |
| tree | b7a92fb67a98dff17e9e35a0166f223cc9354ac3 /src/soc/sifive/fu540/clint.c | |
| parent | 533efb23083afd721d4c268ce0ee8e863e13689a (diff) | |
soc/amd/phoenix: Add build rules to enable CBFS verification
Add SPI flash RO ranges to be verified by GSC in order to enable CBFS
verification. Also with CBFS verification enabled, CBFS metadata is
more than 64 bytes. So configure the offset of amdfw_a/b to 128 bytes -
next address aligned to 64 bytes.
BUG=b:277087492
TEST=Build and boot to OS in Myst with and without CBFS verification
enabled.
Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78233
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/sifive/fu540/clint.c')
0 files changed, 0 insertions, 0 deletions