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authorAaron Durbin <adurbin@chromium.org>2016-09-13 12:31:57 -0500
committerAaron Durbin <adurbin@chromium.org>2016-09-14 15:40:16 +0200
commit9e81540b85c6d06c7c3c63447b92f09590f032d1 (patch)
tree34e120d03c5c03bd6af4181f05e42b92202a58ce /src/soc/samsung/exynos5420/wakeup.c
parent9a23569ee14f828f950516bb71ec7eab99521b61 (diff)
soc/intel/apollolake: initialize GNVS structure to 0
The code was not previously initializing the GNVS structure to all 0's in the ACPI write tables path. Fix this and also rearrange the ordering of updating the fields to only handle the chip_info specific bits till last such that most of the structure is filled in prior to bailing out in the case of a bad devicetree. Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16597 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/samsung/exynos5420/wakeup.c')
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