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authorMartin Roth <martin.roth@se-eng.com>2014-12-07 14:59:11 -0700
committerMartin Roth <gaumless@gmail.com>2014-12-08 05:39:07 +0100
commit1fc2ba5e6d85f3c7eef00a7e6b0b3ee1352fbfa9 (patch)
treec943575806918a817060c0fc638625b42294733e /src/soc/samsung/exynos5420/setup.h
parentde7ed6fc7cdb3f55894e613bdc0c394fa8f57494 (diff)
samsung/exynos5420: Spelling Fixes
Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7703 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/soc/samsung/exynos5420/setup.h')
-rw-r--r--src/soc/samsung/exynos5420/setup.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/samsung/exynos5420/setup.h b/src/soc/samsung/exynos5420/setup.h
index 63e40a8f0f..e0a7d1b0a8 100644
--- a/src/soc/samsung/exynos5420/setup.h
+++ b/src/soc/samsung/exynos5420/setup.h
@@ -790,7 +790,7 @@ struct exynos5_phy_control;
#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
#define CTRL_ATGATE (1 << 6)
-#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
+#define FP_RSYNC (1 << 3) /* Force DLL resynchronization */
/* Driver strength for CK, CKE, CS & CA */
#define IMP_OUTPUT_DRV_40_OHM 0x5
@@ -809,7 +809,7 @@ struct exynos5_phy_control;
struct mem_timings;
-/* Errors that we can encourter in low-level setup */
+/* Errors that we can encounter in low-level setup */
enum {
SETUP_ERR_OK,
SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,