armv7: Move Exynos from 'cpu' to 'soc'.

The Exynos family and most ARM products are SoC, not just CPU.

We used to put ARM code in src/cpu to avoid polluting the code base for what was
essentially an experiment at the time. Now that it's past the experimental phase
and we're going to see more SoCs (including intel/baytrail) in coreboot.

Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c
Reviewed-on: https://chromium-review.googlesource.com/170891
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6739
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 36 insertions, 0 deletions

diff --git a/src/soc/samsung/exynos5420/mct.c b/src/soc/samsung/exynos5420/mct.c
new file mode 100644
index 0000000000..bbb90e49bb
--- /dev/null
+++ b/src/soc/samsung/exynos5420/mct.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include "clk.h"
+
+uint64_t mct_raw_value(void)
+{
+	uint64_t upper = readl(&exynos_mct->g_cnt_u);
+	uint64_t lower = readl(&exynos_mct->g_cnt_l);
+
+	return (upper << 32) | lower;
+}
+
+void mct_start(void)
+{
+	writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
+		&exynos_mct->g_tcon);
+}