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authorJulius Werner <jwerner@chromium.org>2014-10-20 13:18:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-07 18:48:30 +0200
commit80af442cd21eaa924840614b00c082b9b29abff1 (patch)
tree2fa3894a6a1a6e9d3e426275755b1614cf84abb5 /src/soc/samsung/exynos5420/include
parent1ed0c8c0b221962855b6f547cc663c506b9cb5c6 (diff)
exynos5420: Change all SoC headers to <soc/headername.h> system
This patch aligns exynos5420 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Peach_Pit. Change-Id: If97b40101d3541a81bca302a9bd64b84a04ff24a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 570ca9ed6337d622781f37184b2cd7209de0083f Original-Change-Id: I338559564e57bdc5202d34c7173ce0d075ad2afc Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224501 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9324 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/samsung/exynos5420/include')
-rw-r--r--src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h39
-rw-r--r--src/soc/samsung/exynos5420/include/soc/clk.h762
-rw-r--r--src/soc/samsung/exynos5420/include/soc/cpu.h99
-rw-r--r--src/soc/samsung/exynos5420/include/soc/dmc.h414
-rw-r--r--src/soc/samsung/exynos5420/include/soc/dp.h1431
-rw-r--r--src/soc/samsung/exynos5420/include/soc/dsim.h110
-rw-r--r--src/soc/samsung/exynos5420/include/soc/fimd.h217
-rw-r--r--src/soc/samsung/exynos5420/include/soc/gpio.h550
-rw-r--r--src/soc/samsung/exynos5420/include/soc/i2c.h25
-rw-r--r--src/soc/samsung/exynos5420/include/soc/i2s-regs.h142
-rw-r--r--src/soc/samsung/exynos5420/include/soc/memlayout.ld49
-rw-r--r--src/soc/samsung/exynos5420/include/soc/periph.h72
-rw-r--r--src/soc/samsung/exynos5420/include/soc/pinmux.h53
-rw-r--r--src/soc/samsung/exynos5420/include/soc/power.h113
-rw-r--r--src/soc/samsung/exynos5420/include/soc/setup.h886
-rw-r--r--src/soc/samsung/exynos5420/include/soc/spi.h98
-rw-r--r--src/soc/samsung/exynos5420/include/soc/sysreg.h43
-rw-r--r--src/soc/samsung/exynos5420/include/soc/tmu.h135
-rw-r--r--src/soc/samsung/exynos5420/include/soc/trustzone.h82
-rw-r--r--src/soc/samsung/exynos5420/include/soc/uart.h42
-rw-r--r--src/soc/samsung/exynos5420/include/soc/usb.h147
-rw-r--r--src/soc/samsung/exynos5420/include/soc/wakeup.h43
22 files changed, 5552 insertions, 0 deletions
diff --git a/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h
new file mode 100644
index 0000000000..4df61d53f2
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
+#define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
+
+/* These are pointers to function pointers. Double indirection! */
+static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
+static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
+static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
+static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
+static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
+
+#define SECONDARY_BASE_BOOT_USB 0xfeed0002
+static u32 * const iram_secondary_base = (u32 *)0x02020018;
+
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC 0x8
+#define OM_STAT_SPI 0x14
+#define OM_STAT_MASK 0x7f
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H */
diff --git a/src/soc/samsung/exynos5420/include/soc/clk.h b/src/soc/samsung/exynos5420/include/soc/clk.h
new file mode 100644
index 0000000000..ca1d721f85
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/clk.h
@@ -0,0 +1,762 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_CLK_H
+#define CPU_SAMSUNG_EXYNOS5420_CLK_H
+
+#include <soc/cpu.h>
+#include <soc/dmc.h>
+#include <soc/pinmux.h>
+#include <stdint.h>
+
+enum periph_id;
+
+/* This master list of PLLs is ordered arbitrarily. */
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+#define BPLL 5
+#define RPLL 6
+#define SPLL 7
+#define CPLL 8
+#define DPLL 9
+#define IPLL 10
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
+
+/**
+ * get the clk frequency of the required peripheral
+ *
+ * @param peripheral Peripheral id
+ *
+ * @return frequency of the peripheral clk
+ */
+unsigned long clock_get_periph_rate(enum periph_id peripheral);
+
+#define MCT_HZ 24000000
+
+/*
+ * Set mshci controller instances clock divider
+ *
+ * @param enum periph_id instance of the mshci controller
+ *
+ * Return 0 if ok else -1
+ */
+int clock_set_mshci(enum periph_id peripheral);
+
+/*
+ * Set dwmci controller instances clock divider
+ *
+ * @param enum periph_id instance of the dwmci controller
+ *
+ * Return 0 if ok else -1
+ */
+int clock_set_dwmci(enum periph_id peripheral);
+
+/*
+ * Sets the epll clockrate
+ *
+ * @param rate Required clock rate to the prescaler in Hz
+ *
+ * Return 0 if ok else -1
+ */
+int clock_epll_set_rate(unsigned long rate);
+
+/*
+ * selects the clk source for I2S MCLK
+ */
+void clock_select_i2s_clk_source(void);
+
+/*
+ * Set prescaler division based on input and output frequency
+ * for i2s audio clock
+ *
+ * @param src_frq Source frequency in Hz
+ * @param dst_frq Required MCLK frequency in Hz
+ *
+ * Return 0 if ok else -1
+ */
+int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
+
+struct exynos5420_clock {
+ uint32_t apll_lock; /* 0x10010000 */
+ uint8_t res1[0xfc];
+ uint32_t apll_con0;
+ uint32_t apll_con1;
+ uint8_t res2[0xf8];
+ uint32_t clk_src_cpu;
+ uint8_t res3[0x1fc];
+ uint32_t clk_mux_stat_cpu;
+ uint8_t res4[0xfc];
+ uint32_t clk_div_cpu0; /* 0x10010500 */
+ uint32_t clk_div_cpu1;
+ uint8_t res5[0xf8];
+ uint32_t clk_div_stat_cpu0;
+ uint32_t clk_div_stat_cpu1;
+ uint8_t res6[0xf8];
+ uint32_t clk_gate_bus_cpu;
+ uint8_t res7[0xfc];
+ uint32_t clk_gate_sclk_cpu;
+ uint8_t res8[0x1fc];
+ uint32_t clkout_cmu_cpu; /* 0x10010a00 */
+ uint32_t clkout_cmu_cpu_div_stat;
+ uint8_t res9[0x5f8];
+ uint32_t armclk_stopctrl;
+ uint8_t res10[0x4];
+ uint32_t arm_ema_ctrl;
+ uint32_t arm_ema_status;
+ uint8_t res11[0x10];
+ uint32_t pwr_ctrl;
+ uint32_t pwr_ctrl2;
+ uint8_t res12[0xd8];
+ uint32_t apll_con0_l8; /* 0x1001100 */
+ uint32_t apll_con0_l7;
+ uint32_t apll_con0_l6;
+ uint32_t apll_con0_l5;
+ uint32_t apll_con0_l4;
+ uint32_t apll_con0_l3;
+ uint32_t apll_con0_l2;
+ uint32_t apll_con0_l1;
+ uint32_t iem_control;
+ uint8_t res13[0xdc];
+ uint32_t apll_con1_l8; /* 0x10011200 */
+ uint32_t apll_con1_l7;
+ uint32_t apll_con1_l6;
+ uint32_t apll_con1_l5;
+ uint32_t apll_con1_l4;
+ uint32_t apll_con1_l3;
+ uint32_t apll_con1_l2;
+ uint32_t apll_con1_l1;
+ uint8_t res14[0xe0];
+ uint32_t clkdiv_iem_l8;
+ uint32_t clkdiv_iem_l7; /* 0x10011304 */
+ uint32_t clkdiv_iem_l6;
+ uint32_t clkdiv_iem_l5;
+ uint32_t clkdiv_iem_l4;
+ uint32_t clkdiv_iem_l3;
+ uint32_t clkdiv_iem_l2;
+ uint32_t clkdiv_iem_l1;
+ uint8_t res15[0xe0];
+ uint32_t l2_status;
+ uint8_t res16[0x0c];
+ uint32_t cpu_status; /* 0x10011410 */
+ uint8_t res17[0x0c];
+ uint32_t ptm_status;
+ uint8_t res18[0xbdc];
+ uint32_t cmu_cpu_spare0;
+ uint32_t cmu_cpu_spare1;
+ uint32_t cmu_cpu_spare2;
+ uint32_t cmu_cpu_spare3;
+ uint32_t cmu_cpu_spare4;
+ uint8_t res19[0x1fdc];
+ uint32_t cmu_cpu_version;
+ uint8_t res20[0x20c];
+ uint32_t clk_src_cperi0; /* 0x10014200 */
+ uint32_t clk_src_cperi1;
+ uint8_t res21[0xf8];
+ uint32_t clk_src_mask_cperi;
+ uint8_t res22[0x100];
+ uint32_t clk_mux_stat_cperi1;
+ uint8_t res23[0xfc];
+ uint32_t clk_div_cperi1;
+ uint8_t res24[0xfc];
+ uint32_t clk_div_stat_cperi1;
+ uint8_t res25[0xf8];
+ uint32_t clk_gate_bus_cperi0; /* 0x10014700 */
+ uint32_t clk_gate_bus_cperi1;
+ uint8_t res26[0xf8];
+ uint32_t clk_gate_sclk_cperi;
+ uint8_t res27[0xfc];
+ uint32_t clk_gate_ip_cperi;
+ uint8_t res28[0xfc];
+ uint32_t clkout_cmu_cperi;
+ uint32_t clkout_cmu_cperi_div_stat;
+ uint8_t res29[0x5f8];
+ uint32_t dcgidx_map0; /* 0x10015000 */
+ uint32_t dcgidx_map1;
+ uint32_t dcgidx_map2;
+ uint8_t res30[0x14];
+ uint32_t dcgperf_map0;
+ uint32_t dcgperf_map1;
+ uint8_t res31[0x18];
+ uint32_t dvcidx_map;
+ uint8_t res32[0x1c];
+ uint32_t freq_cpu;
+ uint32_t freq_dpm;
+ uint8_t res33[0x18];
+ uint32_t dvsemclk_en; /* 0x10015080 */
+ uint32_t maxperf;
+ uint8_t res34[0x2e78];
+ uint32_t cmu_cperi_spare0;
+ uint32_t cmu_cperi_spare1;
+ uint32_t cmu_cperi_spare2;
+ uint32_t cmu_cperi_spare3;
+ uint32_t cmu_cperi_spare4;
+ uint32_t cmu_cperi_spare5;
+ uint32_t cmu_cperi_spare6;
+ uint32_t cmu_cperi_spare7;
+ uint32_t cmu_cperi_spare8;
+ uint8_t res35[0xcc];
+ uint32_t cmu_cperi_version; /* 0x10017ff0 */
+ uint8_t res36[0x50c];
+ uint32_t clk_div_g2d;
+ uint8_t res37[0xfc];
+ uint32_t clk_div_stat_g2d;
+ uint8_t res38[0xfc];
+ uint32_t clk_gate_bus_g2d;
+ uint8_t res39[0xfc];
+ uint32_t clk_gate_ip_g2d;
+ uint8_t res40[0x1fc];
+ uint32_t clkout_cmu_g2d;
+ uint32_t clkout_cmu_g2d_div_stat;/* 0x10018a04 */
+ uint8_t res41[0xf8];
+ uint32_t cmu_g2d_spare0;
+ uint32_t cmu_g2d_spare1;
+ uint32_t cmu_g2d_spare2;
+ uint32_t cmu_g2d_spare3;
+ uint32_t cmu_g2d_spare4;
+ uint8_t res42[0x34dc];
+ uint32_t cmu_g2d_version;
+ uint8_t res43[0x30c];
+ uint32_t clk_div_cmu_isp0;
+ uint32_t clk_div_cmu_isp1;
+ uint32_t clk_div_isp2; /* 0x1001c308 */
+ uint8_t res44[0xf4];
+ uint32_t clk_div_stat_cmu_isp0;
+ uint32_t clk_div_stat_cmu_isp1;
+ uint32_t clk_div_stat_isp2;
+ uint8_t res45[0x2f4];
+ uint32_t clk_gate_bus_isp0;
+ uint32_t clk_gate_bus_isp1;
+ uint32_t clk_gate_bus_isp2;
+ uint32_t clk_gate_bus_isp3;
+ uint8_t res46[0xf0];
+ uint32_t clk_gate_ip_isp0;
+ uint32_t clk_gate_ip_isp1;
+ uint8_t res47[0xf8];
+ uint32_t clk_gate_sclk_isp;
+ uint8_t res48[0x0c];
+ uint32_t mcuisp_pwr_ctrl; /* 0x1001c910 */
+ uint8_t res49[0x0ec];
+ uint32_t clkout_cmu_isp;
+ uint32_t clkout_cmu_isp_div_stat;
+ uint8_t res50[0xf8];
+ uint32_t cmu_isp_spare0;
+ uint32_t cmu_isp_spare1;
+ uint32_t cmu_isp_spare2;
+ uint32_t cmu_isp_spare3;
+ uint8_t res51[0x34e0];
+ uint32_t cmu_isp_version;
+ uint8_t res52[0x2c];
+ uint32_t cpll_lock; /* 10020020 */
+ uint8_t res53[0xc];
+ uint32_t dpll_lock;
+ uint8_t res54[0xc];
+ uint32_t epll_lock;
+ uint8_t res55[0xc];
+ uint32_t rpll_lock;
+ uint8_t res56[0xc];
+ uint32_t ipll_lock;
+ uint8_t res57[0xc];
+ uint32_t spll_lock;
+ uint8_t res58[0xc];
+ uint32_t vpll_lock;
+ uint8_t res59[0xc];
+ uint32_t mpll_lock;
+ uint8_t res60[0x8c];
+ uint32_t cpll_con0; /* 10020120 */
+ uint32_t cpll_con1;
+ uint32_t dpll_con0;
+ uint32_t dpll_con1;
+ uint32_t epll_con0;
+ uint32_t epll_con1;
+ uint32_t epll_con2;
+ uint8_t res601[0x4];
+ uint32_t rpll_con0;
+ uint32_t rpll_con1;
+ uint32_t rpll_con2;
+ uint8_t res602[0x4];
+ uint32_t ipll_con0;
+ uint32_t ipll_con1;
+ uint8_t res61[0x8];
+ uint32_t spll_con0;
+ uint32_t spll_con1;
+ uint8_t res62[0x8];
+ uint32_t vpll_con0;
+ uint32_t vpll_con1;
+ uint8_t res63[0x8];
+ uint32_t mpll_con0;
+ uint32_t mpll_con1;
+ uint8_t res64[0x78];
+ uint32_t clk_src_top0; /* 0x10020200 */
+ uint32_t clk_src_top1;
+ uint32_t clk_src_top2;
+ uint32_t clk_src_top3;
+ uint32_t clk_src_top4;
+ uint32_t clk_src_top5;
+ uint32_t clk_src_top6;
+ uint32_t clk_src_top7;
+ uint8_t res65[0xc];
+ uint32_t clk_src_disp10; /* 0x1002022c */
+ uint8_t res66[0x10];
+ uint32_t clk_src_mau;
+ uint32_t clk_src_fsys;
+ uint8_t res67[0x8];
+ uint32_t clk_src_peric0;
+ uint32_t clk_src_peric1;
+ uint8_t res68[0x18];
+ uint32_t clk_src_isp;
+ uint8_t res69[0x0c];
+ uint32_t clk_src_top10;
+ uint32_t clk_src_top11;
+ uint32_t clk_src_top12;
+ uint8_t res70[0x74];
+ uint32_t clk_src_mask_top0;
+ uint32_t clk_src_mask_top1;
+ uint32_t clk_src_mask_top2;
+ uint8_t res71[0x10];
+ uint32_t clk_src_mask_top7;
+ uint8_t res72[0xc];
+ uint32_t clk_src_mask_disp10; /* 0x1002032c */
+ uint8_t res73[0x4];
+ uint32_t clk_src_mask_mau;
+ uint8_t res74[0x8];
+ uint32_t clk_src_mask_fsys;
+ uint8_t res75[0xc];
+ uint32_t clk_src_mask_peric0;
+ uint32_t clk_src_mask_peric1;
+ uint8_t res76[0x18];
+ uint32_t clk_src_mask_isp;
+ uint8_t res77[0x8c];
+ uint32_t clk_mux_stat_top0; /* 0x10020400 */
+ uint32_t clk_mux_stat_top1;
+ uint32_t clk_mux_stat_top2;
+ uint32_t clk_mux_stat_top3;
+ uint32_t clk_mux_stat_top4;
+ uint32_t clk_mux_stat_top5;
+ uint32_t clk_mux_stat_top6;
+ uint32_t clk_mux_stat_top7;
+ uint8_t res78[0x60];
+ uint32_t clk_mux_stat_top10;
+ uint32_t clk_mux_stat_top11;
+ uint32_t clk_mux_stat_top12;
+ uint8_t res79[0x74];
+ uint32_t clk_div_top0; /* 0x10020500 */
+ uint32_t clk_div_top1;
+ uint32_t clk_div_top2;
+ uint8_t res80[0x20];
+ uint32_t clk_div_disp10;
+ uint8_t res81[0x14];
+ uint32_t clk_div_mau;
+ uint32_t clk_div_fsys0;
+ uint32_t clk_div_fsys1;
+ uint32_t clk_div_fsys2;
+ uint8_t res82[0x4];
+ uint32_t clk_div_peric0;
+ uint32_t clk_div_peric1;
+ uint32_t clk_div_peric2;
+ uint32_t clk_div_peric3;
+ uint32_t clk_div_peric4; /* 0x10020568 */
+ uint8_t res83[0x14];
+ uint32_t clk_div_isp0;
+ uint32_t clk_div_isp1;
+ uint8_t res84[0x8];
+ uint32_t clkdiv2_ratio;
+ uint8_t res850[0xc];
+ uint32_t clkdiv4_ratio;
+ uint8_t res85[0x5c];
+ uint32_t clk_div_stat_top0;
+ uint32_t clk_div_stat_top1;
+ uint32_t clk_div_stat_top2;
+ uint8_t res86[0x20];
+ uint32_t clk_div_stat_disp10;
+ uint8_t res87[0x14];
+ uint32_t clk_div_stat_mau; /* 0x10020644 */
+ uint32_t clk_div_stat_fsys0;
+ uint32_t clk_div_stat_fsys1;
+ uint32_t clk_div_stat_fsys2;
+ uint8_t res88[0x4];
+ uint32_t clk_div_stat_peric0;
+ uint32_t clk_div_stat_peric1;
+ uint32_t clk_div_stat_peric2;
+ uint32_t clk_div_stat_peric3;
+ uint32_t clk_div_stat_peric4;
+ uint8_t res89[0x14];
+ uint32_t clk_div_stat_isp0;
+ uint32_t clk_div_stat_isp1;
+ uint8_t res90[0x8];
+ uint32_t clkdiv2_stat0;
+ uint8_t res91[0xc];
+ uint32_t clkdiv4_stat;
+ uint8_t res92[0x5c];
+ uint32_t clk_gate_bus_top; /* 0x10020700 */
+ uint8_t res93[0xc];
+ uint32_t clk_gate_bus_gscl0;
+ uint8_t res94[0xc];
+ uint32_t clk_gate_bus_gscl1;
+ uint8_t res95[0x4];
+ uint32_t clk_gate_bus_disp1;
+ uint8_t res96[0x4];
+ uint32_t clk_gate_bus_wcore;
+ uint32_t clk_gate_bus_mfc;
+ uint32_t clk_gate_bus_g3d;
+ uint32_t clk_gate_bus_gen;
+ uint32_t clk_gate_bus_fsys0;
+ uint32_t clk_gate_bus_fsys1;
+ uint32_t clk_gate_bus_fsys2;
+ uint32_t clk_gate_bus_mscl;
+ uint32_t clk_gate_bus_peric;
+ uint32_t clk_gate_bus_peric1;
+ uint8_t res97[0x8];
+ uint32_t clk_gate_bus_peris0;
+ uint32_t clk_gate_bus_peris1; /* 0x10020764 */
+ uint8_t res98[0x8];
+ uint32_t clk_gate_bus_noc;
+ uint8_t res99[0xac];
+ uint32_t clk_gate_top_sclk_gscl;
+ uint8_t res1000[0x4];
+ uint32_t clk_gate_top_sclk_disp1;
+ uint8_t res100[0x10];
+ uint32_t clk_gate_top_sclk_mau;
+ uint32_t clk_gate_top_sclk_fsys;
+ uint8_t res101[0xc];
+ uint32_t clk_gate_top_sclk_peric;
+ uint8_t res102[0xc];
+ uint32_t clk_gate_top_sclk_cperi;
+ uint8_t res103[0xc];
+ uint32_t clk_gate_top_sclk_isp;
+ uint8_t res104[0x9c];
+ uint32_t clk_gate_ip_gscl0;
+ uint8_t res105[0xc];
+ uint32_t clk_gate_ip_gscl1;
+ uint8_t res106[0x4];
+ uint32_t clk_gate_ip_disp1;
+ uint32_t clk_gate_ip_mfc;
+ uint32_t clk_gate_ip_g3d;
+ uint32_t clk_gate_ip_gen; /* 0x10020934 */
+ uint8_t res107[0xc];
+ uint32_t clk_gate_ip_fsys;
+ uint8_t res108[0x8];
+ uint32_t clk_gate_ip_peric;
+ uint8_t res109[0xc];
+ uint32_t clk_gate_ip_peris;
+ uint8_t res110[0xc];
+ uint32_t clk_gate_ip_mscl;
+ uint8_t res111[0xc];
+ uint32_t clk_gate_ip_block;
+ uint8_t res112[0xc];
+ uint32_t bypass;
+ uint8_t res113[0x6c];
+ uint32_t clkout_cmu_top;
+ uint32_t clkout_cmu_top_div_stat;
+ uint8_t res114[0xf8];
+ uint32_t clkout_top_spare0;
+ uint32_t clkout_top_spare1;
+ uint32_t clkout_top_spare2;
+ uint32_t clkout_top_spare3;
+ uint8_t res115[0x34e0];
+ uint32_t clkout_top_version;
+ uint8_t res116[0xc01c];
+ uint32_t bpll_lock; /* 0x10030010 */
+ uint8_t res117[0xfc];
+ uint32_t bpll_con0;
+ uint32_t bpll_con1;
+ uint8_t res118[0xe8];
+ uint32_t clk_src_cdrex;
+ uint8_t res119[0x1fc];
+ uint32_t clk_mux_stat_cdrex;
+ uint8_t res120[0xfc];
+ uint32_t clk_div_cdrex0;
+ uint32_t clk_div_cdrex1;
+ uint8_t res121[0xf8];
+ uint32_t clk_div_stat_cdrex;
+ uint8_t res1211[0xfc];
+ uint32_t clk_gate_bus_cdrex;
+ uint32_t clk_gate_bus_cdrex1;
+ uint8_t res122[0x1f8];
+ uint32_t clk_gate_ip_cdrex;
+ uint8_t res123[0x10];
+ uint32_t dmc_freq_ctrl; /* 0x10030914 */
+ uint8_t res124[0x4];
+ uint32_t pause;
+ uint32_t ddrphy_lock_ctrl;
+ uint8_t res125[0xdc];
+ uint32_t clkout_cmu_cdrex;
+ uint32_t clkout_cmu_cdrex_div_stat;
+ uint8_t res126[0x8];
+ uint32_t lpddr3phy_ctrl;
+ uint32_t lpddr3phy_con0;
+ uint32_t lpddr3phy_con1;
+ uint32_t lpddr3phy_con2;
+ uint32_t lpddr3phy_con3;
+ uint32_t lpddr3phy_con4;
+ uint32_t lpddr3phy_con5; /* 0x10030a28 */
+ uint32_t pll_div2_sel;
+ uint8_t res127[0xd0];
+ uint32_t cmu_cdrex_spare0;
+ uint32_t cmu_cdrex_spare1;
+ uint32_t cmu_cdrex_spare2;
+ uint32_t cmu_cdrex_spare3;
+ uint32_t cmu_cdrex_spare4;
+ uint8_t res128[0x34dc];
+ uint32_t cmu_cdrex_version; /* 0x10033ff0 */
+ uint8_t res129[0x400c];
+ uint32_t kpll_lock;
+ uint8_t res130[0xfc];
+ uint32_t kpll_con0;
+ uint32_t kpll_con1;
+ uint8_t res131[0xf8];
+ uint32_t clk_src_kfc;
+ uint8_t res132[0x1fc];
+ uint32_t clk_mux_stat_kfc; /* 0x10038400 */
+ uint8_t res133[0xfc];
+ uint32_t clk_div_kfc0;
+ uint8_t res134[0xfc];
+ uint32_t clk_div_stat_kfc0;
+ uint8_t res135[0xfc];
+ uint32_t clk_gate_bus_cpu_kfc;
+ uint8_t res136[0xfc];
+ uint32_t clk_gate_sclk_cpu_kfc;
+ uint8_t res137[0x1fc];
+ uint32_t clkout_cmu_kfc;
+ uint32_t clkout_cmu_kfc_div_stat;/* 0x10038a04 */
+ uint8_t res138[0x5f8];
+ uint32_t armclk_stopctrl_kfc;
+ uint8_t res139[0x4];
+ uint32_t armclk_ema_ctrl_kfc;
+ uint32_t armclk_ema_status_kfc;
+ uint8_t res140[0x10];
+ uint32_t pwr_ctrl_kfc;
+ uint32_t pwr_ctrl2_kfc;
+ uint8_t res141[0xd8];
+ uint32_t kpll_con0_l8;
+ uint32_t kpll_con0_l7;
+ uint32_t kpll_con0_l6;
+ uint32_t kpll_con0_l5;
+ uint32_t kpll_con0_l4;
+ uint32_t kpll_con0_l3;
+ uint32_t kpll_con0_l2;
+ uint32_t kpll_con0_l1;
+ uint32_t iem_control_kfc; /* 0x10039120 */
+ uint8_t res142[0xdc];
+ uint32_t kpll_con1_l8;
+ uint32_t kpll_con1_l7;
+ uint32_t kpll_con1_l6;
+ uint32_t kpll_con1_l5;
+ uint32_t kpll_con1_l4;
+ uint32_t kpll_con1_l3;
+ uint32_t kpll_con1_l2;
+ uint32_t kpll_con1_l1;
+ uint8_t res143[0xe0];
+ uint32_t clkdiv_iem_l8_kfc; /* 0x10039300 */
+ uint32_t clkdiv_iem_l7_kfc;
+ uint32_t clkdiv_iem_l6_kfc;
+ uint32_t clkdiv_iem_l5_kfc;
+ uint32_t clkdiv_iem_l4_kfc;
+ uint32_t clkdiv_iem_l3_kfc;
+ uint32_t clkdiv_iem_l2_kfc;
+ uint32_t clkdiv_iem_l1_kfc;
+ uint8_t res144[0xe0];
+ uint32_t l2_status_kfc;
+ uint8_t res145[0xc];
+ uint32_t cpu_status_kfc; /* 0x10039410 */
+ uint8_t res146[0xc];
+ uint32_t ptm_status_kfc;
+ uint8_t res147[0xbdc];
+ uint32_t cmu_kfc_spare0;
+ uint32_t cmu_kfc_spare1;
+ uint32_t cmu_kfc_spare2;
+ uint32_t cmu_kfc_spare3;
+ uint32_t cmu_kfc_spare4;
+ uint8_t res148[0x1fdc];
+ uint32_t cmu_kfc_version; /* 0x1003bff0 */
+};
+check_member(exynos5420_clock, cmu_kfc_version, 0x2bff0);
+
+static struct exynos5420_clock * const exynos_clock =
+ (void *)EXYNOS5_CLOCK_BASE;
+
+struct exynos5_mct {
+ uint32_t mct_cfg;
+ uint8_t reserved0[0xfc];
+ uint32_t g_cnt_l;
+ uint32_t g_cnt_u;
+ uint8_t reserved1[0x8];
+ uint32_t g_cnt_wstat;
+ uint8_t reserved2[0xec];
+ uint32_t g_comp0_l;
+ uint32_t g_comp0_u;
+ uint32_t g_comp0_addr_incr;
+ uint8_t reserved3[0x4];
+ uint32_t g_comp1_l;
+ uint32_t g_comp1_u;
+ uint32_t g_comp1_addr_incr;
+ uint8_t reserved4[0x4];
+ uint32_t g_comp2_l;
+ uint32_t g_comp2_u;
+ uint32_t g_comp2_addr_incr;
+ uint8_t reserved5[0x4];
+ uint32_t g_comp3_l;
+ uint32_t g_comp3_u;
+ uint32_t g_comp3_addr_incr;
+ uint8_t reserved6[0x4];
+ uint32_t g_tcon;
+ uint32_t g_int_cstat;
+ uint32_t g_int_enb;
+ uint32_t g_wstat;
+ uint8_t reserved7[0xb0];
+ uint32_t l0_tcntb;
+ uint32_t l0_tcnto;
+ uint32_t l0_icntb;
+ uint32_t l0_icnto;
+ uint32_t l0_frcntb;
+ uint32_t l0_frcnto;
+ uint8_t reserved8[0x8];
+ uint32_t l0_tcon;
+ uint8_t reserved9[0xc];
+ uint32_t l0_int_cstat;
+ uint32_t l0_int_enb;
+ uint8_t reserved10[0x8];
+ uint32_t l0_wstat;
+ uint8_t reserved11[0xbc];
+ uint32_t l1_tcntb;
+ uint32_t l1_tcnto;
+ uint32_t l1_icntb;
+ uint32_t l1_icnto;
+ uint32_t l1_frcntb;
+ uint32_t l1_frcnto;
+ uint8_t reserved12[0x8];
+ uint32_t l1_tcon;
+ uint8_t reserved13[0xc];
+ uint32_t l1_int_cstat;
+ uint32_t l1_int_enb;
+ uint8_t reserved14[0x8];
+ uint32_t l1_wstat;
+};
+check_member(exynos5_mct, l1_wstat, 0x440);
+
+static struct exynos5_mct * const exynos_mct =
+ (void *)EXYNOS5_MULTI_CORE_TIMER_BASE;
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
+#define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */
+#define TIMEOUT_EPLL_LOCK 1000
+
+#define AUDIO_0_RATIO_MASK 0x0f
+#define AUDIO_1_RATIO_MASK 0x0f
+
+#define CLK_SRC_PERIC1 0x254
+#define AUDIO1_SEL_MASK 0xf
+#define CLK_SRC_AUDIOCDCLK1 0x0
+#define CLK_SRC_XXTI 0x1
+#define CLK_SRC_SCLK_EPLL 0x7
+
+/* CON0 bit-fields */
+#define EPLL_CON0_MDIV_MASK 0x1ff
+#define EPLL_CON0_PDIV_MASK 0x3f
+#define EPLL_CON0_SDIV_MASK 0x7
+#define EPLL_CON0_LOCKED_SHIFT 29
+#define EPLL_CON0_MDIV_SHIFT 16
+#define EPLL_CON0_PDIV_SHIFT 8
+#define EPLL_CON0_SDIV_SHIFT 0
+#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
+#define EPLL_CON0_LOCK_DET_EN_MASK 1
+
+/* structure for epll configuration used in audio clock configuration */
+struct st_epll_con_val {
+ unsigned int freq_out; /* frequency out */
+ unsigned int en_lock_det; /* enable lock detect */
+ unsigned int m_div; /* m divider value */
+ unsigned int p_div; /* p divider value */
+ unsigned int s_div; /* s divider value */
+ unsigned int k_dsm; /* k value of delta signal modulator */
+};
+
+/**
+ * Low-level function to set the clock pre-ratio for a peripheral
+ *
+ * @param periph_id Peripheral ID of peripheral to change
+ * @param divisor New divisor for this peripheral's clock
+ */
+void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor);
+
+/**
+ * Low-level function to set the clock ratio for a peripheral
+ *
+ * @param periph_id Peripheral ID of peripheral to change
+ * @param divisor New divisor for this peripheral's clock
+ */
+void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor);
+
+/**
+ * Low-level function that selects the best clock scalars for a given rate and
+ * sets up the given peripheral's clock accordingly.
+ *
+ * @param periph_id Peripheral ID of peripheral to change
+ * @param rate Desired clock rate in Hz
+ *
+ * @return zero on success, negative on error
+ */
+int clock_set_rate(enum periph_id periph_id, unsigned int rate);
+
+/* Clock gate unused IP */
+void clock_gate(void);
+
+void mct_start(void);
+uint64_t mct_raw_value(void);
+
+/* These are the ratio's for configuring ARM clock */
+struct arm_clk_ratios {
+ unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */
+
+ unsigned int apll_mdiv;
+ unsigned int apll_pdiv;
+ unsigned int apll_sdiv;
+
+ unsigned int arm2_ratio;
+ unsigned int apll_ratio;
+ unsigned int pclk_dbg_ratio;
+ unsigned int atb_ratio;
+ unsigned int periph_ratio;
+ unsigned int acp_ratio;
+ unsigned int cpud_ratio;
+ unsigned int arm_ratio;
+};
+
+/**
+ * Get the clock ratios for CPU configuration
+ *
+ * @return pointer to the clock ratios that we should use
+ */
+struct arm_clk_ratios *get_arm_clk_ratios(void);
+
+/*
+ * Initialize clock for the device
+ */
+struct mem_timings;
+void system_clock_init(void);
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/cpu.h b/src/soc/samsung/exynos5420/include/soc/cpu.h
new file mode 100644
index 0000000000..bea7f1e1e2
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/cpu.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_CPU_H
+#define CPU_SAMSUNG_EXYNOS5420_CPU_H
+
+#include <arch/io.h>
+#include <symbols.h>
+
+#define EXYNOS5_SRAM_BASE 0x02020000
+
+/* Base address registers */
+#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 /* Z0 */
+#define EXYNOS5_PRO_ID 0x10000000
+#define EXYNOS5_CLOCK_BASE 0x10010000
+#define EXYNOS5_POWER_BASE 0x10040000
+#define EXYNOS5_SYSREG_BASE 0x10050000
+#define EXYNOS5_TZPC1_DECPROT1SET 0x10110810
+#define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000
+#define EXYNOS5_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5_ACE_SFR_BASE 0x10830000
+#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
+#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
+#define EXYNOS5420_DMC_DREXI_0 0x10C20000
+#define EXYNOS5420_DMC_DREXI_1 0x10C30000
+#define EXYNOS5420_DMC_TZASC_0 0x10D40000
+#define EXYNOS5420_DMC_TZASC_1 0x10D50000
+#define EXYNOS5420_USB_DRD0_XHCI_BASE 0x12000000
+#define EXYNOS5420_USB_DRD0_DWC3_BASE 0x1200C100
+#define EXYNOS5420_USB_DRD0_PHY_BASE 0x12100000
+#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
+#define EXYNOS5_USB_HOST_PHY_BASE 0x12130000
+#define EXYNOS5_MMC_BASE 0x12200000
+#define EXYNOS5_MSHC_BASE 0x12240000
+#define EXYNOS5_SROMC_BASE 0x12250000
+#define EXYNOS5420_USB_DRD1_XHCI_BASE 0x12400000
+#define EXYNOS5420_USB_DRD1_DWC3_BASE 0x1240C100
+#define EXYNOS5420_USB_DRD1_PHY_BASE 0x12500000
+#define EXYNOS5_UART0_BASE 0x12C00000
+#define EXYNOS5_UART1_BASE 0x12C10000
+#define EXYNOS5_UART2_BASE 0x12C20000
+#define EXYNOS5_UART3_BASE 0x12C30000
+#define EXYNOS5_I2C_BASE 0x12C60000
+#define EXYNOS5_SPI0_BASE 0x12D20000
+#define EXYNOS5_SPI1_BASE 0x12D30000
+#define EXYNOS5_SPI2_BASE 0x12D40000
+#define EXYNOS5_I2S_BASE 0x12D60000
+#define EXYNOS5420_I2C_8910_BASE 0x12E00000
+#define EXYNOS5_UART_ISP_BASE 0x13190000
+#define EXYNOS5_SPI_ISP_BASE 0x131A0000
+#define EXYNOS5420_GPIO_PART1_BASE 0x13400000 /* Y0 */
+#define EXYNOS5420_GPIO_PART2_BASE 0x13400C00 /* X0..3 */
+#define EXYNOS5420_GPIO_PART3_BASE 0x13410000 /* C0..4, D1, Y0..6 */
+#define EXYNOS5420_GPIO_PART4_BASE 0x14000000 /* E0..1, F0..1, G0..2, J4 */
+#define EXYNOS5420_GPIO_PART5_BASE 0x14010000 /* A0..2, B0..4, H0 */
+#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
+#define EXYNOS5_DP0_BASE 0x14510000
+#define EXYNOS5_DP1_BASE 0x145B0000
+
+/* Marker values stored at the bottom of IRAM stack by SPL */
+#define EXYNOS5_SPL_MARKER 0xb004f1a9 /* hexspeak word: bootflag */
+
+#define RST_FLAG_VAL 0xfcba0d10
+
+#define EXYNOS5_SPI_NUM_CONTROLLERS 5
+#define EXYNOS_I2C_MAX_CONTROLLERS 8
+
+extern struct tmu_info exynos5420_tmu_info;
+
+/* TODO clean up defines. */
+#define FB_SIZE_KB 4096
+#define RAM_BASE_KB ((uintptr_t)_dram/KiB)
+#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
+
+static inline u32 get_fb_base_kb(void)
+{
+ return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;
+}
+
+/* Procedures to setup Exynos5420 CPU */
+void exynos5420_config_smp(void);
+
+#endif /* _EXYNOS5420_CPU_H */
diff --git a/src/soc/samsung/exynos5420/include/soc/dmc.h b/src/soc/samsung/exynos5420/include/soc/dmc.h
new file mode 100644
index 0000000000..bc0751de89
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/dmc.h
@@ -0,0 +1,414 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_DMC_H
+#define CPU_SAMSUNG_EXYNOS5420_DMC_H
+
+#define DMC_INTERLEAVE_SIZE 0x1f
+
+#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT 28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
+#ifndef __ASSEMBLER__
+
+#include <soc/cpu.h>
+
+struct exynos5_dmc {
+ uint32_t concontrol;
+ uint32_t memcontrol;
+ uint32_t cgcontrol;
+ uint32_t memconfig1;
+ uint32_t directcmd;
+ uint32_t prechconfig0;
+ uint32_t phycontrol0;
+ uint32_t prechconfig1;
+ uint8_t res1[0x8];
+ uint32_t pwrdnconfig; /* 0x0028*/
+ uint32_t timingpzq;
+ uint32_t timingref;
+ uint32_t timingrow;
+ uint32_t timingdata;
+ uint32_t timingpower;
+ uint32_t phystatus;
+ uint8_t res2[0x4];
+ uint32_t chipstatus_ch0; /* 0x0048 */
+ uint32_t chipstatus_ch1;
+ uint8_t res3[0x4];
+ uint32_t mrstatus;
+ uint8_t res4[0x8];
+ uint32_t qoscontrol0; /* 0x0060 */
+ uint8_t resr5[0x4];
+ uint32_t qoscontrol1;
+ uint8_t res6[0x4];
+ uint32_t qoscontrol2;
+ uint8_t res7[0x4];
+ uint32_t qoscontrol3;
+ uint8_t res8[0x4];
+ uint32_t qoscontrol4;
+ uint8_t res9[0x4];
+ uint32_t qoscontrol5;
+ uint8_t res10[0x4];
+ uint32_t qoscontrol6;
+ uint8_t res11[0x4];
+ uint32_t qoscontrol7;
+ uint8_t res12[0x4];
+ uint32_t qoscontrol8;
+ uint8_t res13[0x4];
+ uint32_t qoscontrol9;
+ uint8_t res14[0x4];
+ uint32_t qoscontrol10;
+ uint8_t res15[0x4];
+ uint32_t qoscontrol11;
+ uint8_t res16[0x4];
+ uint32_t qoscontrol12;
+ uint8_t res17[0x4];
+ uint32_t qoscontrol13;
+ uint8_t res18[0x4];
+ uint32_t qoscontrol14;
+ uint8_t res19[0x4];
+ uint32_t qoscontrol15;
+ uint8_t res20[0x4];
+ uint32_t timing_set_sw; /* 0x00e0 */
+ uint32_t timingrow1;
+ uint32_t timingdata1;
+ uint32_t timingpower1;
+ uint32_t ivcontrol;
+ uint32_t wrtra_config;
+ uint32_t rdlvl_config;
+ uint8_t res21[0x4];
+ uint32_t brbrsvcontrol; /* 0x0100*/
+ uint32_t brbrsvconfig;
+ uint32_t brbqosconfig;
+ uint32_t membaseconfig0;
+ uint32_t membaseconfig1; /* 0x0110 */
+ uint8_t res22[0xc];
+ uint32_t wrlvl_config0; /* 0x0120 */
+ uint32_t wrlvl_config1;
+ uint32_t wrlvl_status;
+ uint8_t res23[0x4];
+ uint32_t perevcontrol; /* 0x0130 */
+ uint32_t perev0config;
+ uint32_t perev1config;
+ uint32_t perev2config;
+ uint32_t perev3config;
+ uint8_t res22a[0xc];
+ uint32_t ctrl_io_rdata_ch0;
+ uint32_t ctrl_io_rdata_ch1;
+ uint8_t res23a[0x8];
+ uint32_t cacal_config0;
+ uint32_t cacal_config1;
+ uint32_t cacal_status;
+ uint8_t res24[0x94];
+ uint32_t emergent_config0; /* 0x0200 */
+ uint32_t emergent_config1;
+ uint8_t res25[0x8];
+ uint32_t bp_control0;
+ uint32_t bp_control0_r;
+ uint32_t bp_control0_w;
+ uint8_t res26[0x4];
+ uint32_t bp_control1;
+ uint32_t bp_control1_r;
+ uint32_t bp_control1_w;
+ uint8_t res27[0x4];
+ uint32_t bp_control2;
+ uint32_t bp_control2_r;
+ uint32_t bp_control2_w;
+ uint8_t res28[0x4];
+ uint32_t bp_control3;
+ uint32_t bp_control3_r;
+ uint32_t bp_control3_w;
+ uint8_t res29[0xb4];
+ uint32_t winconfig_odt_w; /* 0x0300 */
+ uint8_t res30[0x4];
+ uint32_t winconfig_ctrl_read;
+ uint32_t winconfig_ctrl_gate;
+ uint8_t res31[0xdcf0];
+ uint32_t pmnc_ppc;
+ uint8_t res32[0xc];
+ uint32_t cntens_ppc;
+ uint8_t res33[0xc];
+ uint32_t cntenc_ppc;
+ uint8_t res34[0xc];
+ uint32_t intens_ppc;
+ uint8_t res35[0xc];
+ uint32_t intenc_ppc;
+ uint8_t res36[0xc];
+ uint32_t flag_ppc; /* 0xe050 */
+ uint8_t res37[0xac];
+ uint32_t ccnt_ppc;
+ uint8_t res38[0xc];
+ uint32_t pmcnt0_ppc;
+ uint8_t res39[0xc];
+ uint32_t pmcnt1_ppc;
+ uint8_t res40[0xc];
+ uint32_t pmcnt2_ppc;
+ uint8_t res41[0xc];
+ uint32_t pmcnt3_ppc; /* 0xe140 */
+} __attribute__((packed));
+check_member(exynos5_dmc, pmcnt3_ppc, 0xe140);
+
+static struct exynos5_dmc * const exynos_drex0 = (void *)EXYNOS5420_DMC_DREXI_0;
+static struct exynos5_dmc * const exynos_drex1 = (void *)EXYNOS5420_DMC_DREXI_1;
+
+struct exynos5_phy_control {
+ uint32_t phy_con0;
+ uint32_t phy_con1;
+ uint32_t phy_con2;
+ uint32_t phy_con3;
+ uint32_t phy_con4;
+ uint8_t res1[4];
+ uint32_t phy_con6;
+ uint8_t res2[4];
+ uint32_t phy_con8;
+ uint32_t phy_con9;
+ uint32_t phy_con10;
+ uint8_t res3[4];
+ uint32_t phy_con12;
+ uint32_t phy_con13;
+ uint32_t phy_con14;
+ uint32_t phy_con15;
+ uint32_t phy_con16;
+ uint8_t res4[4]; /* NOT a mistake. Yes, it doesn't make sense. */
+ uint32_t phy_con17;
+ uint32_t phy_con18;
+ uint32_t phy_con19;
+ uint32_t phy_con20;
+ uint32_t phy_con21;
+ uint32_t phy_con22;
+ uint32_t phy_con23;
+ uint32_t phy_con24;
+ uint32_t phy_con25;
+ uint32_t phy_con26;
+ uint32_t phy_con27;
+ uint32_t phy_con28;
+ uint32_t phy_con29;
+ uint32_t phy_con30;
+ uint32_t phy_con31;
+ uint32_t phy_con32;
+ uint32_t phy_con33;
+ uint32_t phy_con34;
+ uint32_t phy_con35;
+ uint32_t phy_con36;
+ uint32_t phy_con37;
+ uint32_t phy_con38;
+ uint32_t phy_con39;
+ uint32_t phy_con40;
+ uint32_t phy_con41;
+ uint32_t phy_con42;
+} __attribute__((packed));
+check_member(exynos5_phy_control, phy_con42, 0xac);
+
+static struct exynos5_phy_control * const exynos_phy0_control =
+ (void *)EXYNOS5_DMC_PHY0_BASE;
+static struct exynos5_phy_control * const exynos_phy1_control =
+ (void *)EXYNOS5_DMC_PHY1_BASE;
+
+struct exynos5_tzasc {
+ uint8_t res1[0xf00];
+ uint32_t membaseconfig0;
+ uint32_t membaseconfig1;
+ uint8_t res2[0x8];
+ uint32_t memconfig0;
+ uint32_t memconfig1;
+} __attribute__((packed));
+
+static struct exynos5_tzasc * const exynos_tzasc0 =
+ (void *)EXYNOS5420_DMC_TZASC_0;
+static struct exynos5_tzasc * const exynos_tzasc1 =
+ (void *)EXYNOS5420_DMC_TZASC_1;
+
+enum ddr_mode {
+ /* This is in order of ctrl_ddr_mode values. Do not change. */
+ DDR_MODE_DDR2 = 0x0,
+ DDR_MODE_DDR3 = 0x1,
+ DDR_MODE_LPDDR2 = 0x2,
+ DDR_MODE_LPDDR3 = 0x3,
+
+ DDR_MODE_COUNT,
+};
+
+/* For reasons unknown, people are in the habit of taking a 32-bit
+ * field with 2 possible values and packing it with, say, 2 bits. A
+ * non-robust encoding, using only 2 bits of a 32-bit field, is
+ * incredibly difficult to deal with when things go wrong, because
+ * there are a lot of things that get expressed as 0, 1, or 2. If
+ * you're scanning with jtag or dumping memory it is really hard to
+ * tell when you've hit the beginning of the struct. So, let's be a
+ * bit smart here. First, while it's common to let the enum count
+ * entries for you, when there are two of them, we can do the
+ * counting. And, let's set the values to something we can easily scan
+ * for in memory. Since '1' and '2' are rather common, we pick
+ * something that's actually of some value when things go wrong. This
+ * setup motivated by a use case: something's going wrong and having a
+ * manuf name of '1' or '2' is completely useless!
+ */
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA = 0xe7b1da,
+ MEM_MANUF_SAMSUNG = 0x5a5096,
+
+ MEM_MANUF_COUNT = 2, // fancy that.
+};
+
+enum {
+ MEM_TIMINGS_MSR_COUNT = 5,
+};
+
+
+/* These are the memory timings for a particular memory type and speed */
+struct mem_timings {
+ enum mem_manuf mem_manuf; /* Memory manufacturer */
+ enum ddr_mode mem_type; /* Memory type */
+ unsigned int frequency_mhz; /* Frequency of memory in MHz */
+
+ /* Here follow the timing parameters for the selected memory */
+ uint8_t apll_mdiv;
+ uint8_t apll_pdiv;
+ uint8_t apll_sdiv;
+ uint8_t mpll_mdiv;
+ uint8_t mpll_pdiv;
+ uint8_t mpll_sdiv;
+ uint8_t cpll_mdiv;
+ uint8_t cpll_pdiv;
+ uint8_t cpll_sdiv;
+ uint8_t gpll_pdiv;
+ uint16_t gpll_mdiv;
+ uint8_t gpll_sdiv;
+ uint8_t epll_mdiv;
+ uint8_t epll_pdiv;
+ uint8_t epll_sdiv;
+ uint8_t vpll_mdiv;
+ uint8_t vpll_pdiv;
+ uint8_t vpll_sdiv;
+ uint8_t bpll_mdiv;
+ uint8_t bpll_pdiv;
+ uint8_t bpll_sdiv;
+ uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */
+ uint8_t pclk_cdrex_ratio;
+ unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
+
+ unsigned int timing_ref;
+ unsigned int timing_row;
+ unsigned int timing_data;
+ unsigned int timing_power;
+
+ /* DQS, DQ, DEBUG offsets */
+ unsigned int phy0_dqs;
+ unsigned int phy1_dqs;
+ unsigned int phy0_dq;
+ unsigned int phy1_dq;
+ uint8_t phy0_tFS;
+ uint8_t phy1_tFS;
+ uint8_t phy0_pulld_dqs;
+ uint8_t phy1_pulld_dqs;
+
+ uint8_t lpddr3_ctrl_phy_reset;
+ uint8_t ctrl_start_point;
+ uint8_t ctrl_inc;
+ uint8_t ctrl_start;
+ uint8_t ctrl_dll_on;
+ uint8_t ctrl_ref;
+
+ uint8_t ctrl_force;
+ uint8_t ctrl_rdlat;
+ uint8_t ctrl_bstlen;
+
+ uint8_t fp_resync;
+ uint8_t iv_size;
+ uint8_t dfi_init_start;
+ uint8_t aref_en;
+
+ uint8_t rd_fetch;
+
+ uint8_t zq_mode_dds;
+ uint8_t zq_mode_term;
+ uint8_t zq_mode_noterm; /* 1 to allow termination disable */
+
+ unsigned int memcontrol;
+ unsigned int memconfig;
+
+ unsigned int membaseconfig0;
+ unsigned int membaseconfig1;
+ unsigned int prechconfig_tp_cnt;
+ unsigned int dpwrdn_cyc;
+ unsigned int dsref_cyc;
+ unsigned int concontrol;
+ /* Channel and Chip Selection */
+ uint8_t dmc_channels; /* number of memory channels */
+ uint8_t chips_per_channel; /* number of chips per channel */
+ uint8_t chips_to_configure; /* number of chips to configure */
+ uint8_t send_zq_init; /* 1 to send this command */
+ unsigned int impedance; /* drive strength impedance */
+ uint8_t gate_leveling_enable; /* check gate leveling is enabled */
+};
+
+/**
+ * Get the correct memory timings for our selected memory type and speed.
+ *
+ * @return pointer to the memory timings that we should use
+ */
+struct mem_timings *get_mem_timings(void);
+
+#endif
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/dp.h b/src/soc/samsung/exynos5420/include/soc/dp.h
new file mode 100644
index 0000000000..73bc9b21fe
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/dp.h
@@ -0,0 +1,1431 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Register map for Exynos5 DP */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_DP_H
+#define CPU_SAMSUNG_EXYNOS5420_DP_H
+
+#include <soc/cpu.h>
+
+/* DSIM register map */
+struct exynos_dp {
+ u8 res1[0x10];
+ u32 tx_version;
+ u32 tx_sw_reset;
+ u32 func_en1;
+ u32 func_en2;
+ u32 video_ctl1;
+ u32 video_ctl2;
+ u32 video_ctl3;
+ u32 video_ctl4;
+ u32 color_blue_cb;
+ u32 color_green_y;
+ u32 color_red_cr;
+ u32 video_ctl8;
+ u8 res2[0x4];
+ u32 video_ctl10;
+ u32 total_ln_cfg_l;
+ u32 total_ln_cfg_h;
+ u32 active_ln_cfg_l;
+ u32 active_ln_cfg_h;
+ u32 vfp_cfg;
+ u32 vsw_cfg;
+ u32 vbp_cfg;
+ u32 total_pix_cfg_l;
+ u32 total_pix_cfg_h;
+ u32 active_pix_cfg_l;
+ u32 active_pix_cfg_h;
+ u32 hfp_cfg_l;
+ u32 hfp_cfg_h;
+ u32 hsw_cfg_l;
+ u32 hsw_cfg_h;
+ u32 hbp_cfg_l;
+ u32 hbp_cfg_h;
+ u32 video_status;
+ u32 total_ln_sta_l;
+ u32 total_ln_sta_h;
+ u32 active_ln_sta_l;
+ u32 active_ln_sta_h;
+
+ u32 vfp_sta;
+ u32 vsw_sta;
+ u32 vbp_sta;
+
+ u32 total_pix_sta_l;
+ u32 total_pix_sta_h;
+ u32 active_pix_sta_l;
+ u32 active_pix_sta_h;
+
+ u32 hfp_sta_l;
+ u32 hfp_sta_h;
+ u32 hsw_sta_l;
+ u32 hsw_sta_h;
+ u32 hbp_sta_l;
+ u32 hbp_sta_h;
+
+ u8 res3[0x288];
+
+ u32 lane_map;
+ u8 res4[0x10];
+ u32 analog_ctl1;
+ u32 analog_ctl2;
+ u32 analog_ctl3;
+
+ u32 pll_filter_ctl1;
+ u32 amp_tuning_ctl;
+ u8 res5[0xc];
+
+ u32 aux_hw_retry_ctl;
+ u8 res6[0x2c];
+ u32 int_state;
+ u32 common_int_sta1;
+ u32 common_int_sta2;
+ u32 common_int_sta3;
+ u32 common_int_sta4;
+ u8 res7[0x8];
+
+ u32 int_sta;
+ u8 res8[0x1c];
+ u32 int_ctl;
+ u8 res9[0x200];
+ u32 sys_ctl1;
+ u32 sys_ctl2;
+ u32 sys_ctl3;
+ u32 sys_ctl4;
+ u32 vid_ctl;
+ u8 res10[0x2c];
+ u32 pkt_send_ctl;
+ u8 res[0x4];
+ u32 hdcp_ctl;
+ u8 res11[0x34];
+ u32 link_bw_set;
+
+ u32 lane_count_set;
+ u32 training_ptn_set;
+ u32 ln0_link_training_ctl;
+ u32 ln1_link_training_ctl;
+ u32 ln2_link_training_ctl;
+ u32 ln3_link_training_ctl;
+ u32 dn_spread_ctl;
+ u32 hw_link_training_ctl;
+ u8 res12[0x1c];
+
+ u32 debug_ctl;
+ u32 hpd_deglitch_l;
+ u32 hpd_deglitch_h;
+
+ u8 res13[0x14];
+ u32 link_debug_ctl;
+
+ u8 res14[0x1c];
+
+ u32 m_vid0;
+ u32 m_vid1;
+ u32 m_vid2;
+ u32 n_vid0;
+ u32 n_vid1;
+ u32 n_vid2;
+ u32 m_vid_mon;
+ u32 pll_ctl;
+ u32 phy_pd;
+ u32 phy_test;
+ u8 res15[0x8];
+
+ u32 video_fifo_thrd;
+ u8 res16[0x8];
+ u32 audio_margin;
+
+ u32 dn_spread_ctl1;
+ u32 dn_spread_ctl2;
+ u8 res17[0x18];
+ u32 m_cal_ctl;
+ u32 m_vid_gen_filter_th;
+ u8 res18[0x10];
+ u32 m_aud_gen_filter_th;
+ u8 res50[0x4];
+
+ u32 aux_ch_sta;
+ u32 aux_err_num;
+ u32 aux_ch_defer_ctl;
+ u32 aux_rx_comm;
+ u32 buffer_data_ctl;
+
+ u32 aux_ch_ctl1;
+ u32 aux_addr_7_0;
+ u32 aux_addr_15_8;
+ u32 aux_addr_19_16;
+ u32 aux_ch_ctl2;
+ u8 res19[0x18];
+ u32 buf_data0;
+ u8 res20[0x3c];
+
+ u32 soc_general_ctl;
+ u8 res21[0x8c];
+ u32 crc_con;
+ u32 crc_result;
+ u8 res22[0x8];
+
+ u32 common_int_mask1;
+ u32 common_int_mask2;
+ u32 common_int_mask3;
+ u32 common_int_mask4;
+ u32 int_sta_mask1;
+ u32 int_sta_mask2;
+ u32 int_sta_mask3;
+ u32 int_sta_mask4;
+ u32 int_sta_mask;
+ u32 crc_result2;
+ u32 scrambler_reset_cnt;
+
+ u32 pn_inv;
+ u32 psr_config;
+ u32 psr_command0;
+ u32 psr_command1;
+ u32 psr_crc_mon0;
+ u32 psr_crc_mon1;
+
+ u8 res24[0x30];
+ u32 phy_bist_ctrl;
+ u8 res25[0xc];
+ u32 phy_ctrl;
+ u8 res26[0x1c];
+ u32 test_pattern_gen_en;
+ u32 test_pattern_gen_ctrl;
+};
+check_member(exynos_dp, phy_ctrl, 0x924);
+
+static struct exynos_dp * const exynos_dp0 = (void *)EXYNOS5_DP0_BASE;
+static struct exynos_dp * const exynos_dp1 = (void *)EXYNOS5_DP1_BASE;
+
+/* For DP VIDEO CTL 1 */
+#define VIDEO_EN_MASK (0x01 << 7)
+#define VIDEO_MUTE_MASK (0x01 << 6)
+
+/* For DP VIDEO CTL 4 */
+#define VIDEO_BIST_MASK (0x1 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_1 */
+#define SEL_BG_NEW_BANDGAP (0x0 << 6)
+#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6)
+#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4)
+#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4)
+#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4)
+#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
+#define SWING_A_30PER_G_INCREASE (0x1 << 3)
+#define SWING_A_30PER_G_NORMAL (0x0 << 3)
+
+/* EXYNOS_DP_ANALOG_CTL_2 */
+#define CPREG_BLEED (0x1 << 4)
+#define SEL_24M (0x1 << 3)
+#define TX_DVDD_BIT_1_0000V (0x3 << 0)
+#define TX_DVDD_BIT_1_0625V (0x4 << 0)
+#define TX_DVDD_BIT_1_1250V (0x5 << 0)
+
+/* EXYNOS_DP_ANALOG_CTL_3 */
+#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
+#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
+#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5)
+#define SEL_CURRENT_DEFAULT (0x0 << 3)
+#define VCO_BIT_000_MICRO (0x0 << 0)
+#define VCO_BIT_200_MICRO (0x1 << 0)
+#define VCO_BIT_300_MICRO (0x2 << 0)
+#define VCO_BIT_400_MICRO (0x3 << 0)
+#define VCO_BIT_500_MICRO (0x4 << 0)
+#define VCO_BIT_600_MICRO (0x5 << 0)
+#define VCO_BIT_700_MICRO (0x6 << 0)
+#define VCO_BIT_900_MICRO (0x7 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+#define PD_RING_OSC (0x1 << 6)
+#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
+#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4)
+#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4)
+#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4)
+#define TX_CUR1_1X (0x0 << 2)
+#define TX_CUR1_2X (0x1 << 2)
+#define TX_CUR1_3X (0x2 << 2)
+#define TX_CUR_1_MA (0x0 << 0)
+#define TX_CUR_2_MA (0x1 << 0)
+#define TX_CUR_3_MA (0x2 << 0)
+#define TX_CUR_4_MA (0x3 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_2 */
+#define CH3_AMP_0_MV (0x3 << 12)
+#define CH2_AMP_0_MV (0x3 << 8)
+#define CH1_AMP_0_MV (0x3 << 4)
+#define CH0_AMP_0_MV (0x3 << 0)
+
+/* EXYNOS_DP_PLL_CTL */
+#define DP_PLL_PD (0x1 << 7)
+#define DP_PLL_RESET (0x1 << 6)
+#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
+#define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
+#define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
+
+/* EXYNOS_DP_INT_CTL */
+#define SOFT_INT_CTRL (0x1 << 2)
+#define INT_POL (0x1 << 0)
+
+/* DP TX SW RESET */
+#define RESET_DP_TX (0x01 << 0)
+
+/* DP FUNC_EN_1 */
+#define MASTER_VID_FUNC_EN_N (0x1 << 7)
+#define SLAVE_VID_FUNC_EN_N (0x1 << 5)
+#define AUD_FIFO_FUNC_EN_N (0x1 << 4)
+#define AUD_FUNC_EN_N (0x1 << 3)
+#define HDCP_FUNC_EN_N (0x1 << 2)
+#define CRC_FUNC_EN_N (0x1 << 1)
+#define SW_FUNC_EN_N (0x1 << 0)
+
+/* DP FUNC_EN_2 */
+#define SSC_FUNC_EN_N (0x1 << 7)
+#define AUX_FUNC_EN_N (0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
+
+/* EXYNOS_DP_PHY_PD */
+#define PHY_PD (0x1 << 5)
+#define AUX_PD (0x1 << 4)
+#define CH3_PD (0x1 << 3)
+#define CH2_PD (0x1 << 2)
+#define CH1_PD (0x1 << 1)
+#define CH0_PD (0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_1 */
+#define VSYNC_DET (0x1 << 7)
+#define PLL_LOCK_CHG (0x1 << 6)
+#define SPDIF_ERR (0x1 << 5)
+#define SPDIF_UNSTBL (0x1 << 4)
+#define VID_FORMAT_CHG (0x1 << 3)
+#define AUD_CLK_CHG (0x1 << 2)
+#define VID_CLK_CHG (0x1 << 1)
+#define SW_INT (0x1 << 0)
+
+/* EXYNOS_DP_DEBUG_CTL */
+#define PLL_LOCK (0x1 << 4)
+#define F_PLL_LOCK (0x1 << 3)
+#define PLL_LOCK_CTRL (0x1 << 2)
+
+/* EXYNOS_DP_FUNC_EN_2 */
+#define SSC_FUNC_EN_N (0x1 << 7)
+#define AUX_FUNC_EN_N (0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_4 */
+#define PSR_ACTIVE (0x1 << 7)
+#define PSR_INACTIVE (0x1 << 6)
+#define SPDIF_BI_PHASE_ERR (0x1 << 5)
+#define HOTPLUG_CHG (0x1 << 2)
+#define HPD_LOST (0x1 << 1)
+#define PLUG (0x1 << 0)
+
+/* EXYNOS_DP_INT_STA */
+#define INT_HPD (0x1 << 6)
+#define HW_TRAINING_FINISH (0x1 << 5)
+#define RPLY_RECEIV (0x1 << 1)
+#define AUX_ERR (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS (0x1 << 6)
+#define F_HPD (0x1 << 5)
+#define HPD_CTRL (0x1 << 4)
+#define HDCP_RDY (0x1 << 3)
+#define STRM_VALID (0x1 << 2)
+#define F_VALID (0x1 << 1)
+#define VALID_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
+#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
+#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
+#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
+#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
+#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
+#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
+
+/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+#define DEFER_CTRL_EN (0x1 << 7)
+#define DEFER_COUNT(x) (((x) & 0x7f) << 0)
+
+#define COMMON_INT_MASK_1 (0)
+#define COMMON_INT_MASK_2 (0)
+#define COMMON_INT_MASK_3 (0)
+#define COMMON_INT_MASK_4 (0)
+#define INT_STA_MASK (0)
+
+/* EXYNOS_DP_BUFFER_DATA_CTL */
+#define BUF_CLR (0x1 << 7)
+#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
+
+/* EXYNOS_DP_AUX_ADDR_7_0 */
+#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_15_8 */
+#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_19_16 */
+#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
+
+/* EXYNOS_DP_AUX_CH_CTL_1 */
+#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
+#define AUX_TX_COMM_MASK (0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
+#define AUX_TX_COMM_MOT (0x1 << 2)
+#define AUX_TX_COMM_WRITE (0x0 << 0)
+#define AUX_TX_COMM_READ (0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_CTL_2 */
+#define ADDR_ONLY (0x1 << 1)
+#define AUX_EN (0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_STA */
+#define AUX_BUSY (0x1 << 4)
+#define AUX_STATUS_MASK (0xf << 0)
+
+/* EXYNOS_DP_AUX_RX_COMM */
+#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
+#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
+
+/* EXYNOS_DP_PHY_TEST */
+#define MACRO_RST (0x1 << 5)
+#define CH1_TEST (0x1 << 1)
+#define CH0_TEST (0x1 << 0)
+
+/* EXYNOS_DP_TRAINING_PTN_SET */
+#define SCRAMBLER_TYPE (0x1 << 9)
+#define HW_LINK_TRAINING_PATTERN (0x1 << 8)
+#define SCRAMBLING_DISABLE (0x1 << 5)
+#define SCRAMBLING_ENABLE (0x0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
+#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
+
+/* EXYNOS_DP_TOTAL_LINE_CFG */
+#define TOTAL_LINE_CFG_L(x) ((x) & 0xff)
+#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff)
+#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff)
+#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff)
+#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff)
+#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
+
+#define H_F_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+#define H_B_PORCH_CFG_L(x) ((x) & 0xff)
+#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
+
+/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5)
+#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_0_SHIFT (3)
+#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2)
+#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5)
+#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_1_SHIFT (3)
+#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2)
+#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5)
+#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_2_SHIFT (3)
+#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2)
+#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */
+#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5)
+#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3)
+#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3)
+#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3)
+#define PRE_EMPHASIS_SET_3_SHIFT (3)
+#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3)
+#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3)
+#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2)
+#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0)
+#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0)
+#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3)
+#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0)
+#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_10 */
+#define FORMAT_SEL (0x1 << 4)
+#define INTERACE_SCAN_CFG (0x1 << 2)
+#define INTERACE_SCAN_CFG_SHIFT (2)
+#define VSYNC_POLARITY_CFG (0x1 << 1)
+#define V_S_POLARITY_CFG_SHIFT (1)
+#define HSYNC_POLARITY_CFG (0x1 << 0)
+#define H_S_POLARITY_CFG_SHIFT (0)
+
+/* EXYNOS_DP_SOC_GENERAL_CTL */
+#define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
+#define AUDIO_MODE_MASTER_MODE (0x0 << 8)
+#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
+#define VIDEO_MASTER_CLK_SEL (0x1 << 2)
+#define VIDEO_MASTER_MODE_EN (0x1 << 1)
+#define VIDEO_MODE_MASK (0x1 << 0)
+#define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
+#define VIDEO_MODE_MASTER_MODE (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_1 */
+#define VIDEO_EN (0x1 << 7)
+#define HDCP_VIDEO_MUTE (0x1 << 6)
+
+/* EXYNOS_DP_VIDEO_CTL_2 */
+#define IN_D_RANGE_MASK (0x1 << 7)
+#define IN_D_RANGE_SHIFT (7)
+#define IN_D_RANGE_CEA (0x1 << 7)
+#define IN_D_RANGE_VESA (0x0 << 7)
+#define IN_BPC_MASK (0x7 << 4)
+#define IN_BPC_SHIFT (4)
+#define IN_BPC_12_BITS (0x3 << 4)
+#define IN_BPC_10_BITS (0x2 << 4)
+#define IN_BPC_8_BITS (0x1 << 4)
+#define IN_BPC_6_BITS (0x0 << 4)
+#define IN_COLOR_F_MASK (0x3 << 0)
+#define IN_COLOR_F_SHIFT (0)
+#define IN_COLOR_F_YCBCR444 (0x2 << 0)
+#define IN_COLOR_F_YCBCR422 (0x1 << 0)
+#define IN_COLOR_F_RGB (0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_3 */
+#define IN_YC_COEFFI_MASK (0x1 << 7)
+#define IN_YC_COEFFI_SHIFT (7)
+#define IN_YC_COEFFI_ITU709 (0x1 << 7)
+#define IN_YC_COEFFI_ITU601 (0x0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT (4)
+#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_EN */
+#define TEST_PATTERN_GEN_EN (0x1 << 0)
+#define TEST_PATTERN_GEN_DIS (0x0 << 0)
+
+/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */
+#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0)
+#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0)
+#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_4 */
+#define BIST_EN (0x1 << 3)
+#define BIST_WIDTH_MASK (0x1 << 2)
+#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2)
+#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2)
+#define BIST_TYPE_MASK (0x3 << 0)
+#define BIST_TYPE_COLOR_BAR (0x0 << 0)
+#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0)
+#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0)
+
+/* EXYNOS_DP_SYS_CTL_1 */
+#define DET_STA (0x1 << 2)
+#define FORCE_DET (0x1 << 1)
+#define DET_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_2 */
+#define CHA_CRI(x) (((x) & 0xf) << 4)
+#define CHA_STA (0x1 << 2)
+#define FORCE_CHA (0x1 << 1)
+#define CHA_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS (0x1 << 6)
+#define F_HPD (0x1 << 5)
+#define HPD_CTRL (0x1 << 4)
+#define HDCP_RDY (0x1 << 3)
+#define STRM_VALID (0x1 << 2)
+#define F_VALID (0x1 << 1)
+#define VALID_CTRL (0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_4 */
+#define FIX_M_AUD (0x1 << 4)
+#define ENHANCED (0x1 << 3)
+#define FIX_M_VID (0x1 << 2)
+#define M_VID_UPDATE_CTRL (0x3 << 0)
+
+/* EXYNOS_M_VID_X */
+#define M_VID0_CFG(x) ((x) & 0xff)
+#define M_VID1_CFG(x) (((x) >> 8) & 0xff)
+#define M_VID2_CFG(x) (((x) >> 16) & 0xff)
+
+/* EXYNOS_M_VID_X */
+#define N_VID0_CFG(x) ((x) & 0xff)
+#define N_VID1_CFG(x) (((x) >> 8) & 0xff)
+#define N_VID2_CFG(x) (((x) >> 16) & 0xff)
+
+/* DPCD_TRAINING_PATTERN_SET */
+#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
+#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
+#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
+#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
+#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
+
+/* Definition for DPCD Register */
+#define DPCD_DPCD_REV (0x0000)
+#define DPCD_MAX_LINK_RATE (0x0001)
+#define DPCD_MAX_LANE_COUNT (0x0002)
+#define DPCD_LINK_BW_SET (0x0100)
+#define DPCD_LANE_COUNT_SET (0x0101)
+#define DPCD_TRAINING_PATTERN_SET (0x0102)
+#define DPCD_TRAINING_LANE0_SET (0x0103)
+#define DPCD_LANE0_1_STATUS (0x0202)
+#define DPCD_LN_ALIGN_UPDATED (0x0204)
+#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
+#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
+#define DPCD_TEST_REQUEST (0x0218)
+#define DPCD_TEST_RESPONSE (0x0260)
+#define DPCD_TEST_EDID_CHECKSUM (0x0261)
+#define DPCD_SINK_POWER_STATE (0x0600)
+
+/* DPCD_TEST_REQUEST */
+#define DPCD_TEST_EDID_READ (0x1 << 2)
+
+/* DPCD_TEST_RESPONSE */
+#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
+
+/* DPCD_SINK_POWER_STATE */
+#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
+#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR (0x50)
+#define I2C_E_EDID_DEVICE_ADDR (0x30)
+#define EDID_BLOCK_LENGTH (0x80)
+#define EDID_HEADER_PATTERN (0x00)
+#define EDID_EXTENSION_FLAG (0x7e)
+#define EDID_CHECKSUM (0x7f)
+
+/* DPCD_LANE0_1_STATUS */
+#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6)
+#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5)
+#define DPCD_LANE1_CR_DONE (0x1 << 4)
+#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2)
+#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1)
+#define DPCD_LANE0_CR_DONE (0x1 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE0_1 */
+#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0)
+
+/* DPCD_ADJUST_REQUEST_LANE2_3 */
+#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6)
+#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6)
+#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4)
+#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4)
+#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2)
+#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2)
+#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0)
+
+/* DPCD_LANE_COUNT_SET */
+#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
+#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f)
+
+/* DPCD_LANE_ALIGN__STATUS_UPDATED */
+#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
+#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
+#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
+
+/* DPCD_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3)
+#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0)
+#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0)
+
+#define DPCD_REQ_ADJ_SWING (0x00)
+#define DPCD_REQ_ADJ_EMPHASIS (0x01)
+
+#define DP_LANE_STAT_CR_DONE (0x01 << 0)
+#define DP_LANE_STAT_CE_DONE (0x01 << 1)
+#define DP_LANE_STAT_SYM_LOCK (0x01 << 2)
+
+struct exynos_fb {
+ u32 vidcon0;
+ u32 vidcon1;
+ u32 vidcon2;
+ u32 vidcon3;
+ u32 vidtcon0;
+ u32 vidtcon1;
+ u32 vidtcon2;
+ u32 vidtcon3;
+ u32 wincon0;
+ u32 wincon1;
+ u32 wincon2;
+ u32 wincon3;
+ u32 wincon4;
+
+ u32 winshmap;
+ u32 res1;
+
+ u32 winchmap2;
+ u32 vidosd0a;
+ u32 vidosd0b;
+ u32 vidosd0c;
+ u32 res2;
+
+ u32 vidosd1a;
+ u32 vidosd1b;
+ u32 vidosd1c;
+ u32 vidosd1d;
+
+ u32 vidosd2a;
+ u32 vidosd2b;
+ u32 vidosd2c;
+ u32 vidosd2d;
+
+ u32 vidosd3a;
+ u32 vidosd3b;
+ u32 vidosd3c;
+ u32 res3;
+
+ u32 vidosd4a;
+ u32 vidosd4b;
+ u32 vidosd4c;
+ u32 res4[5];
+
+ u32 vidw00add0b0;
+ u32 vidw00add0b1;
+ u32 vidw01add0b0;
+ u32 vidw01add0b1;
+
+ u32 vidw02add0b0;
+ u32 vidw02add0b1;
+ u32 vidw03add0b0;
+ u32 vidw03add0b1;
+ u32 vidw04add0b0;
+ u32 vidw04add0b1;
+ u32 res5[2];
+
+ u32 vidw00add1b0;
+ u32 vidw00add1b1;
+ u32 vidw01add1b0;
+ u32 vidw01add1b1;
+
+ u32 vidw02add1b0;
+ u32 vidw02add1b1;
+ u32 vidw03add1b0;
+ u32 vidw03add1b1;
+
+ u32 vidw04add1b0;
+ u32 vidw04add1b1;
+ u32 res7[2];
+
+ u32 vidw00add2;
+ u32 vidw01add2;
+ u32 vidw02add2;
+ u32 vidw03add2;
+ u32 vidw04add2;
+ u32 res8[7];
+
+ u32 vidintcon0;
+ u32 vidintcon1;
+ u32 res9[1];
+
+ u32 w1keycon0;
+ u32 w1keycon1;
+ u32 w2keycon0;
+ u32 w2keycon1;
+ u32 w3keycon0;
+ u32 w3keycon1;
+ u32 w4keycon0;
+ u32 w4keycon1;
+
+ u32 w1keyalpha;
+ u32 w2keyalpha;
+ u32 w3keyalpha;
+ u32 w4keyalpha;
+
+ u32 dithmode;
+ u32 res10[2];
+
+ u32 win0map;
+ u32 win1map;
+ u32 win2map;
+ u32 win3map;
+ u32 win4map;
+ u32 res11[1];
+
+ u32 wpalcon_h;
+ u32 wpalcon_l;
+
+ u32 trigcon;
+ u32 res12[2];
+
+ u32 i80ifcona0;
+ u32 i80ifcona1;
+ u32 i80ifconb0;
+ u32 i80ifconb1;
+
+ u32 colorgaincon;
+ u32 res13[2];
+
+ u32 ldi_cmdcon0;
+ u32 ldi_cmdcon1;
+ u32 res14[1];
+
+ /* To be updated */
+
+ u8 res15[156];
+ u32 dualrgb;
+ u8 res16[16];
+ u32 dp_mie_clkcon;
+};
+/* TODO: can't decipher this, someone add a check_member() please */
+
+/* LCD IF register offset */
+#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000
+
+static inline u32 exynos_fimd_get_base_offset(void)
+{
+ return EXYNOS5_LCD_IF_BASE_OFFSET/4;
+}
+
+/*
+ * Register offsets
+*/
+#define EXYNOS_WINCON(x) (x)
+#define EXYNOS_VIDOSD(x) (x * 4)
+#define EXYNOS_BUFFER_OFFSET(x) (x * 2)
+#define EXYNOS_BUFFER_SIZE(x) (x)
+
+/*
+ * Bit Definitions
+*/
+
+/* VIDCON0 */
+#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30)
+#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30)
+#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29)
+#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29)
+#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29)
+#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17)
+#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16)
+#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6)
+#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5)
+#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4)
+#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2)
+#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1)
+#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1)
+#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0)
+#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0)
+
+/* VIDCON1 */
+#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7)
+#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7)
+#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6)
+#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6)
+#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5)
+#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5)
+#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4)
+#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4)
+
+/* VIDCON2 */
+#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23)
+#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23)
+#define EXYNOS_VIDCON2_EN601_MASK (1 << 23)
+#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15)
+#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15)
+#define EXYNOS_VIDCON2_WB_MASK (1 << 15)
+#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12)
+#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8)
+#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7)
+#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7)
+#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7)
+
+/* PRTCON */
+#define EXYNOS_PRTCON_UPDATABLE (0 << 11)
+#define EXYNOS_PRTCON_PROTECT (1 << 11)
+
+/* VIDTCON0 */
+#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0)
+
+/* VIDTCON1 */
+#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0)
+
+/* VIDTCON2 */
+#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
+#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23)
+#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22)
+
+/* Window 0~4 Control - WINCONx */
+#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22)
+#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22)
+#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22)
+#define EXYNOS_WINCON_BUFSEL_0 (0 << 20)
+#define EXYNOS_WINCON_BUFSEL_1 (1 << 20)
+#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20)
+#define EXYNOS_WINCON_BUFSEL_SHIFT (20)
+#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19)
+#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19)
+#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19)
+#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18)
+#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18)
+#define EXYNOS_WINCON_BITSWP_SHIFT (18)
+#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17)
+#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17)
+#define EXYNOS_WINCON_BYTESWP_SHIFT (17)
+#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16)
+#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16)
+#define EXYNOS_WINCON_HAWSWP_SHIFT (16)
+#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15)
+#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15)
+#define EXYNOS_WINCON_WSWP_SHIFT (15)
+#define EXYNOS_WINCON_INRGB_RGB (0 << 13)
+#define EXYNOS_WINCON_INRGB_YUV (1 << 13)
+#define EXYNOS_WINCON_INRGB_MASK (1 << 13)
+#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9)
+#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9)
+#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9)
+#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9)
+#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7)
+#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7)
+#define EXYNOS_WINCON_BLD_PLANE (0 << 6)
+#define EXYNOS_WINCON_BLD_PIXEL (1 << 6)
+#define EXYNOS_WINCON_BLD_MASK (1 << 6)
+#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2)
+#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2)
+#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2)
+#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2)
+#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_SHIFT (2)
+#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1)
+#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1)
+#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1)
+#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0)
+#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0)
+
+/* WINCON1 special */
+#define EXYNOS_WINCON1_VP_DISABLE (0 << 24)
+#define EXYNOS_WINCON1_VP_ENABLE (1 << 24)
+#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23)
+
+/* WINSHMAP */
+#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10)
+#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x))
+#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x))
+
+/* VIDOSDxA, VIDOSDxB */
+#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23)
+#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22)
+
+/* VIDOSD0C, VIDOSDxD */
+#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
+
+/* VIDOSDxC (1~4) */
+#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20)
+#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16)
+#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12)
+#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8)
+#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4)
+#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0)
+#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12)
+#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0)
+
+/* Start Address */
+#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24)
+#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0)
+
+/* End Address */
+#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0)
+
+/* Buffer Size */
+#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
+#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
+#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27)
+#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26)
+
+/* WIN Color Map */
+#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff)
+
+/* VIDINTCON0 */
+#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19)
+#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13)
+#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12)
+#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2)
+#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1)
+#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1)
+#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0)
+#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0)
+#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0)
+
+/* VIDINTCON1 */
+#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5)
+#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2)
+#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1)
+#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0)
+
+/* WINMAP */
+#define EXYNOS_WINMAP_ENABLE (1 << 24)
+
+/* WxKEYCON0 (1~4) */
+#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26)
+#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26)
+#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25)
+#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24)
+#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0)
+
+/* WxKEYCON1 (1~4) */
+#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0)
+
+/* DUALRGB */
+#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0)
+#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0)
+#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0)
+#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0)
+#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2)
+#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2)
+#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4)
+#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16)
+#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16)
+#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18)
+
+/* I80IFCONA0 and I80IFCONA1 */
+#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16)
+#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12)
+#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8)
+#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4)
+#define EXYNOS_RSPOL_LOW (0 << 2)
+#define EXYNOS_RSPOL_HIGH (1 << 2)
+#define EXYNOS_I80IFEN_DISABLE (0 << 0)
+#define EXYNOS_I80IFEN_ENABLE (1 << 0)
+
+/* TRIGCON */
+#define EXYNOS_I80SOFT_TRIG_EN (1 << 0)
+#define EXYNOS_I80START_TRIG (1 << 1)
+#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2)
+
+/* DP_MIE_CLKCON */
+#define EXYNOS_DP_MIE_DISABLE (0 << 0)
+#define EXYNOS_DP_CLK_ENABLE (1 << 1)
+#define EXYNOS_MIE_CLK_ENABLE (3 << 0)
+
+#define DP_TIMEOUT_LOOP_COUNT 1000
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 4
+
+#define EXYNOS_DP_SUCCESS 0
+
+enum {
+ DP_DISABLE,
+ DP_ENABLE,
+};
+
+struct edp_disp_info {
+ char *name;
+ unsigned int h_total;
+ unsigned int h_res;
+ unsigned int h_sync_width;
+ unsigned int h_back_porch;
+ unsigned int h_front_porch;
+ unsigned int v_total;
+ unsigned int v_res;
+ unsigned int v_sync_width;
+ unsigned int v_back_porch;
+ unsigned int v_front_porch;
+ unsigned int v_sync_rate;
+};
+
+struct edp_link_train_info {
+ unsigned int lt_status;
+ unsigned int ep_loop;
+ unsigned int cr_loop[4];
+};
+
+struct edp_video_info {
+ unsigned int master_mode;
+ unsigned int bist_mode;
+ unsigned int bist_pattern;
+ unsigned int h_sync_polarity;
+ unsigned int v_sync_polarity;
+ unsigned int interlaced;
+ unsigned int color_space;
+ unsigned int dynamic_range;
+ unsigned int ycbcr_coeff;
+ unsigned int color_depth;
+};
+
+struct edp_device_info {
+ struct edp_disp_info disp_info;
+ struct edp_link_train_info lt_info;
+ struct edp_video_info video_info;
+
+ /*below info get from panel during training*/
+ u8 lane_bw;
+ u8 lane_cnt;
+ u8 dpcd_rev;
+ /*support enhanced frame cap */
+ u8 dpcd_efc;
+ u8 *raw_edid;
+};
+
+enum analog_power_block {
+ AUX_BLOCK,
+ CH0_BLOCK,
+ CH1_BLOCK,
+ CH2_BLOCK,
+ CH3_BLOCK,
+ ANALOG_TOTAL,
+ POWER_ALL
+};
+
+enum pll_status {
+ PLL_UNLOCKED = 0,
+ PLL_LOCKED
+};
+
+enum {
+ COLOR_RGB,
+ COLOR_YCBCR422,
+ COLOR_YCBCR444
+};
+
+enum {
+ VESA,
+ CEA
+};
+
+enum {
+ COLOR_YCBCR601,
+ COLOR_YCBCR709
+};
+
+enum {
+ COLOR_6,
+ COLOR_8,
+ COLOR_10,
+ COLOR_12
+};
+
+enum {
+ DP_LANE_BW_1_62 = 0x06,
+ DP_LANE_BW_2_70 = 0x0a,
+};
+
+enum {
+ DP_LANE_CNT_1 = 1,
+ DP_LANE_CNT_2 = 2,
+ DP_LANE_CNT_4 = 4,
+};
+
+enum {
+ DP_DPCD_REV_10 = 0x10,
+ DP_DPCD_REV_11 = 0x11,
+};
+
+enum {
+ DP_LT_NONE,
+ DP_LT_START,
+ DP_LT_CR,
+ DP_LT_ET,
+ DP_LT_FINISHED,
+ DP_LT_FAIL,
+};
+
+enum {
+ PRE_EMPHASIS_LEVEL_0,
+ PRE_EMPHASIS_LEVEL_1,
+ PRE_EMPHASIS_LEVEL_2,
+ PRE_EMPHASIS_LEVEL_3,
+};
+
+enum {
+ PRBS7,
+ D10_2,
+ TRAINING_PTN1,
+ TRAINING_PTN2,
+ DP_NONE
+};
+
+enum {
+ VOLTAGE_LEVEL_0,
+ VOLTAGE_LEVEL_1,
+ VOLTAGE_LEVEL_2,
+ VOLTAGE_LEVEL_3,
+};
+
+enum pattern_type {
+ NO_PATTERN,
+ COLOR_RAMP,
+ BALCK_WHITE_V_LINES,
+ COLOR_SQUARE,
+ INVALID_PATTERN,
+ COLORBAR_32,
+ COLORBAR_64,
+ WHITE_GRAY_BALCKBAR_32,
+ WHITE_GRAY_BALCKBAR_64,
+ MOBILE_WHITEBAR_32,
+ MOBILE_WHITEBAR_64
+};
+
+enum {
+ CALCULATED_M,
+ REGISTER_M
+};
+
+enum {
+ VIDEO_TIMING_FROM_CAPTURE,
+ VIDEO_TIMING_FROM_REGISTER
+};
+
+
+struct exynos_dp_platform_data {
+ struct edp_device_info *edp_dev_info;
+};
+
+
+int exynos_init_dp(struct edp_device_info *edp_info);
+
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
+
+void exynos_dp_disable_video_bist(void);
+void exynos_dp_enable_video_mute(unsigned int enable);
+void exynos_dp_reset(void);
+void exynos_dp_enable_sw_func(unsigned int enable);
+unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable);
+unsigned int exynos_dp_get_pll_lock_status(void);
+int exynos_dp_init_analog_func(void);
+void exynos_dp_init_hpd(void);
+void exynos_dp_init_aux(void);
+void exynos_dp_config_interrupt(void);
+unsigned int exynos_dp_get_plug_in_status(void);
+unsigned int exynos_dp_detect_hpd(void);
+unsigned int exynos_dp_start_aux_transaction(void);
+unsigned int exynos_dp_write_byte_to_dpcd(u32 reg_addr,
+ u8 data);
+unsigned int exynos_dp_read_byte_from_dpcd(u32 reg_addr,
+ u8 *data);
+unsigned int exynos_dp_write_bytes_to_dpcd(u32 reg_addr,
+ unsigned int count,
+ u8 data[]);
+u32 exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr,
+ unsigned int count,
+ u8 data[]);
+int exynos_dp_select_i2c_device( u32 device_addr,
+ u32 reg_addr);
+int exynos_dp_read_byte_from_i2c(u32 device_addr,
+ u32 reg_addr, unsigned int *data);
+int exynos_dp_read_bytes_from_i2c(u32 device_addr,
+ u32 reg_addr, unsigned int count,
+ u8 edid[]);
+void exynos_dp_reset_macro(void);
+void exynos_dp_set_link_bandwidth(u8 bwtype);
+u8 exynos_dp_get_link_bandwidth(void);
+void exynos_dp_set_lane_count(u8 count);
+unsigned int exynos_dp_get_lane_count(void);
+u8 exynos_dp_get_lanex_pre_emphasis(u8 lanecnt);
+void exynos_dp_set_lane_pre_emphasis(unsigned int level,
+ u8 lanecnt);
+void exynos_dp_set_lanex_pre_emphasis(u8 request_val,
+ u8 lanecnt);
+void exynos_dp_set_training_pattern(unsigned int pattern);
+void exynos_dp_enable_enhanced_mode(u8 enable);
+void exynos_dp_enable_scrambling(unsigned int enable);
+int exynos_dp_init_video(void);
+void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info);
+void exynos_dp_set_video_color_format(struct edp_video_info *video_info);
+int exynos_dp_config_video_bist(struct edp_device_info *edp_info);
+unsigned int exynos_dp_is_slave_video_stream_clock_on(void);
+void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
+ unsigned int n_value);
+void exynos_dp_set_video_timing_mode(unsigned int type);
+void exynos_dp_enable_video_master(unsigned int enable);
+void exynos_dp_start_video(void);
+unsigned int exynos_dp_is_video_stream_on(void);
+void exynos_dp_set_base_addr(void);
+void dp_phy_control(unsigned int enable);
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/dsim.h b/src/soc/samsung/exynos5420/include/soc/dsim.h
new file mode 100644
index 0000000000..9ad55d71c9
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/dsim.h
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Register map for Exynos5 MIPI-DSIM */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_DSIM_H
+#define CPU_SAMSUNG_EXYNOS5420_DSIM_H
+
+/* DSIM register map */
+struct exynos5_dsim {
+ unsigned int status;
+ unsigned int swrst;
+ unsigned int clkctrl;
+ unsigned int timeout;
+ unsigned int config;
+ unsigned int escmode;
+ unsigned int mdresol;
+ unsigned int mvporch;
+ unsigned int mhporch;
+ unsigned int msync;
+ unsigned int sdresol;
+ unsigned int intsrc;
+ unsigned int intmsk;
+ unsigned int pkthdr;
+ unsigned int payload;
+ unsigned int rxfifo;
+ unsigned int res1;
+ unsigned int fifoctrl;
+ unsigned int res2;
+ unsigned int pllctrl;
+ unsigned int plltmr;
+ unsigned int phyacchr;
+ unsigned int phyacchr1;
+};
+check_member(exynos5_dsim, phyacchr1, 0x54);
+
+#define ENABLE 1
+#define DISABLE 0
+
+#define DSIM_SWRST (1 << 0)
+#define NUM_OF_DAT_LANE_IS_FOUR (3 << 5)
+#define DATA_LANE_0_EN (1 << 0)
+#define DATA_LANE_1_EN (1 << 1)
+#define DATA_LANE_2_EN (1 << 2)
+#define DATA_LANE_3_EN (1 << 3)
+#define CLK_LANE_EN (1 << 4)
+#define ENABLE_ALL_DATA_LANE DATA_LANE_0_EN | \
+ DATA_LANE_1_EN | \
+ DATA_LANE_2_EN | \
+ DATA_LANE_3_EN
+#define MAIN_PIX_FORMAT_OFFSET 12
+#define RGB_565_16_BIT 0x4
+#define VIDEO_MODE (1 << 25)
+#define BURST_MODE (1 << 26)
+
+
+#define DSIM_PHYACCHR_AFC_EN (1 << 14)
+#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5
+
+#define DSIM_PLLCTRL_PMS_OFFSET 1
+#define DSIM_FREQ_BAND_OFFSET 24
+
+#define LANE_ESC_CLK_EN_ALL (0x1f << 19)
+#define BYTE_CLK_EN (1 << 24)
+#define DSIM_ESC_CLK_EN (1 << 28)
+#define TXREQUEST_HS_CLK_ON (1 << 31)
+
+#define LP_MODE_ENABLE (1 << 7)
+#define STOP_STATE_CNT_OFFSET 21
+
+#define MAIN_VBP_OFFSET 0
+#define STABLE_VFP_OFFSET 16
+#define CMD_ALLOW_OFFSET 28
+
+#define MAIN_HBP_OFFSET 0
+#define MAIN_HFP_OFFSET 16
+
+#define MAIN_HSA_OFFSET 0
+#define MAIN_VSA_OFFSET 22
+
+#define MAIN_STANDBY (1 << 31)
+#define MAIN_VRESOL_OFFSET 16
+#define MAIN_HRESOL_OFFSET 0
+
+#define SFR_FIFO_EMPTY (1 << 29)
+
+#define DSIM_PLL_EN_SHIFT (1 << 23)
+#define PLL_STABLE (1 << 31)
+
+#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK (1 << 8)
+#define DSIM_TX_READY_HS_CLK (1 << 10)
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/fimd.h b/src/soc/samsung/exynos5420/include/soc/fimd.h
new file mode 100644
index 0000000000..5997f5b652
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/fimd.h
@@ -0,0 +1,217 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Register map for Exynos5 FIMD */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_FIMD_H
+#define CPU_SAMSUNG_EXYNOS5420_FIMD_H
+
+#include <soc/cpu.h>
+
+/* FIMD register map */
+struct exynos5_fimd {
+ /* This is an incomplete list. Add registers as and when required */
+ u32 vidcon0;
+ u8 res1[0x1c];
+ u32 wincon0;
+ u32 wincon1;
+ u32 wincon2;
+ u32 wincon3;
+ u32 wincon4;
+ u32 shadowcon;
+ u8 res2[0x8];
+ u32 vidosd0a;
+ u32 vidosd0b;
+ u32 vidosd0c;
+ u8 res3[0x54];
+ u32 vidw00add0b0;
+ u8 res4[0x2c];
+ u32 vidw00add1b0;
+ u8 res5[0x2c];
+ u32 vidw00add2;
+ u8 res6[0x3c];
+ u32 w1keycon0;
+ u32 w1keycon1;
+ u32 w2keycon0;
+ u32 w2keycon1;
+ u32 w3keycon0;
+ u32 w3keycon1;
+ u32 w4keycon0;
+ u32 w4keycon1;
+ u8 res7[0x20];
+ u32 win0map;
+ u8 res8[0xdc];
+ u32 blendcon;
+ u8 res9[0x18];
+ u32 dpclkcon;
+};
+check_member(exynos5_fimd, dpclkcon, 0x27c);
+
+#define W0_SHADOW_PROTECT (0x1 << 10)
+#define COMPKEY_F 0xffffff
+#define ENVID_F_ON (0x1 << 0)
+#define ENVID_ON (0x1 << 1)
+#define CLKVAL_F 0xb
+#define CLKVAL_F_OFFSET 6
+
+/*
+ * Structure containing display panel specific data for FIMD
+ */
+struct exynos5_fimd_panel {
+ unsigned int is_dp:1; /* Display Panel interface is eDP */
+ unsigned int is_mipi:1; /* Display Panel interface is MIPI */
+ unsigned int fixvclk:2; /* VCLK hold scheme at data underflow */
+
+ /*
+ * Polarity of the VCLK active edge
+ * 0-falling
+ * 1-rising
+ */
+ unsigned int ivclk:1;
+ unsigned int clkval_f; /* Divider to create pixel clock */
+
+ unsigned int upper_margin; /* Vertical Backporch */
+ unsigned int lower_margin; /* Vertical frontporch */
+ unsigned int vsync; /* Vertical Sync Pulse Width */
+ unsigned int left_margin; /* Horizontal Backporch */
+ unsigned int right_margin; /* Horizontal Frontporch */
+ unsigned int hsync; /* Horizontal Sync Pulse Width */
+ unsigned int xres; /* X Resolution */
+ unsigned int yres; /* Y Resolution */
+};
+
+/* LCDIF Register Map */
+struct exynos5_disp_ctrl {
+ u32 vidout_con;
+ u32 vidcon1;
+ u8 res1[0x8];
+ u32 vidtcon0;
+ u32 vidtcon1;
+ u32 vidtcon2;
+ u32 vidtcon3;
+ u8 res2[0x184];
+ u32 trigcon;
+};
+check_member(exynos5_disp_ctrl, trigcon, 0x1a4);
+
+#define VCLK_RISING_EDGE (1 << 7)
+#define VCLK_RUNNING (1 << 9)
+
+#define CHANNEL0_EN (1 << 0)
+
+#define VSYNC_PULSE_WIDTH_VAL 0x3
+#define VSYNC_PULSE_WIDTH_OFFSET 0
+#define V_FRONT_PORCH_VAL 0x3
+#define V_FRONT_PORCH_OFFSET 8
+#define V_BACK_PORCH_VAL 0x3
+#define V_BACK_PORCH_OFFSET 16
+
+#define HSYNC_PULSE_WIDTH_VAL 0x3
+#define HSYNC_PULSE_WIDTH_OFFSET 0
+#define H_FRONT_PORCH_VAL 0x3
+#define H_FRONT_PORCH_OFFSET 8
+#define H_BACK_PORCH_VAL 0x3
+#define H_BACK_PORCH_OFFSET 16
+
+#define HOZVAL_OFFSET 0
+#define LINEVAL_OFFSET 11
+
+#define BPPMODE_F_RGB_16BIT_565 0x5
+#define BPPMODE_F_OFFSET 2
+#define ENWIN_F_ENABLE (1 << 0)
+#define HALF_WORD_SWAP_EN (1 << 16)
+
+#define OSD_RIGHTBOTX_F_OFFSET 11
+#define OSD_RIGHTBOTY_F_OFFSET 0
+
+#define FIMD_CTRL ((struct exynos_fb *)0x14400000)
+
+/* from u-boot fb.h. It needs to be merged with these dp structs maybe. */
+enum {
+ FIMD_RGB_INTERFACE = 1,
+ FIMD_CPU_INTERFACE = 2,
+};
+
+enum exynos_fb_rgb_mode_t {
+ MODE_RGB_P = 0,
+ MODE_BGR_P = 1,
+ MODE_RGB_S = 2,
+ MODE_BGR_S = 3,
+};
+
+typedef struct vidinfo {
+ u16 vl_col; /* Number of columns (i.e. 640) */
+ u16 vl_row; /* Number of rows (i.e. 480) */
+ u16 vl_width; /* Width of display area in millimeters */
+ u16 vl_height; /* Height of display area in millimeters */
+
+ /* LCD configuration register */
+ u8 vl_freq; /* Frequency */
+ u8 vl_clkp; /* Clock polarity */
+ u8 vl_oep; /* Output Enable polarity */
+ u8 vl_hsp; /* Horizontal Sync polarity */
+ u8 vl_vsp; /* Vertical Sync polarity */
+ u8 vl_dp; /* Data polarity */
+ u8 vl_bpix; /* Bits per pixel */
+
+ /* Horizontal control register. Timing from data sheet */
+ u8 vl_hspw; /* Horz sync pulse width */
+ u8 vl_hfpd; /* Wait before of line */
+ u8 vl_hbpd; /* Wait end of line */
+
+ /* Vertical control register. */
+ u8 vl_vspw; /* Vertical sync pulse width */
+ u8 vl_vfpd; /* Wait before of frame */
+ u8 vl_vbpd; /* Wait end of frame */
+ u8 vl_cmd_allow_len; /* Wait end of frame */
+
+ unsigned int win_id;
+ unsigned int init_delay;
+ unsigned int power_on_delay;
+ unsigned int reset_delay;
+ unsigned int interface_mode;
+ unsigned int mipi_enabled;
+ unsigned int dp_enabled;
+ unsigned int cs_setup;
+ unsigned int wr_setup;
+ unsigned int wr_act;
+ unsigned int wr_hold;
+ unsigned int rgb_mode;
+ unsigned int resolution;
+
+ /* parent clock name(MPLL, EPLL or VPLL) */
+ unsigned int pclk_name;
+ /* ratio value for source clock from parent clock. */
+ unsigned int sclk_div;
+
+ unsigned int dual_lcd_enabled;
+ void *screen_base;
+ void *cmap; /* Points at 8 to 16 bit conversion map. */
+} vidinfo_t;
+
+/* fimd.c */
+void exynos_set_trigger(void);
+int exynos_is_i80_frame_done(void);
+void exynos_fimd_lcd_off(void);
+void exynos_fimd_window_off(unsigned int win_id);
+unsigned long exynos_fimd_calc_fbsize(vidinfo_t *vid);
+void exynos_fimd_lcd_disable(void);
+void exynos_fimd_lcd_init(vidinfo_t *vid);
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/gpio.h b/src/soc/samsung/exynos5420/include/soc/gpio.h
new file mode 100644
index 0000000000..1c6a77b7c4
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/gpio.h
@@ -0,0 +1,550 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_GPIO_H
+#define CPU_SAMSUNG_EXYNOS5420_GPIO_H
+
+#include <soc/cpu.h>
+
+struct gpio_bank {
+ unsigned int con;
+ unsigned int dat;
+ unsigned int pull;
+ unsigned int drv;
+ unsigned int pdn_con;
+ unsigned int pdn_pull;
+ unsigned char res1[8];
+};
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
+
+/* Pin configurations */
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+#define GPIO_IRQ 0xf
+#define GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE 0x0
+#define GPIO_PULL_DOWN 0x1
+#define GPIO_PULL_UP 0x3
+
+/* Drive Strength level */
+#define GPIO_DRV_1X 0x0
+#define GPIO_DRV_3X 0x1
+#define GPIO_DRV_2X 0x2
+#define GPIO_DRV_4X 0x3
+#define GPIO_DRV_FAST 0x0
+#define GPIO_DRV_SLOW 0x1
+
+enum exynos5_gpio_port {
+ EXYNOS5_GPY7 = EXYNOS5420_GPIO_PART1_BASE + 0x0000,
+
+ EXYNOS5_GPX0 = EXYNOS5420_GPIO_PART2_BASE + 0x0000,
+ EXYNOS5_GPX1 = EXYNOS5420_GPIO_PART2_BASE + 0x0020,
+ EXYNOS5_GPX2 = EXYNOS5420_GPIO_PART2_BASE + 0x0040,
+ EXYNOS5_GPX3 = EXYNOS5420_GPIO_PART2_BASE + 0x0060,
+
+ EXYNOS5_GPC0 = EXYNOS5420_GPIO_PART3_BASE + 0x0000,
+ EXYNOS5_GPC1 = EXYNOS5420_GPIO_PART3_BASE + 0x0020,
+ EXYNOS5_GPC2 = EXYNOS5420_GPIO_PART3_BASE + 0x0040,
+ EXYNOS5_GPC3 = EXYNOS5420_GPIO_PART3_BASE + 0x0060,
+ EXYNOS5_GPC4 = EXYNOS5420_GPIO_PART3_BASE + 0x0080,
+
+ EXYNOS5_GPD1 = EXYNOS5420_GPIO_PART3_BASE + 0x00a0,
+
+ EXYNOS5_GPY0 = EXYNOS5420_GPIO_PART3_BASE + 0x00c0,
+ EXYNOS5_GPY1 = EXYNOS5420_GPIO_PART3_BASE + 0x00e0,
+ EXYNOS5_GPY2 = EXYNOS5420_GPIO_PART3_BASE + 0x0100,
+ EXYNOS5_GPY3 = EXYNOS5420_GPIO_PART3_BASE + 0x0120,
+ EXYNOS5_GPY4 = EXYNOS5420_GPIO_PART3_BASE + 0x0140,
+ EXYNOS5_GPY5 = EXYNOS5420_GPIO_PART3_BASE + 0x0160,
+ EXYNOS5_GPY6 = EXYNOS5420_GPIO_PART3_BASE + 0x0180,
+
+ EXYNOS5_GPE0 = EXYNOS5420_GPIO_PART4_BASE + 0x0000,
+ EXYNOS5_GPE1 = EXYNOS5420_GPIO_PART4_BASE + 0x0020,
+
+ EXYNOS5_GPF0 = EXYNOS5420_GPIO_PART4_BASE + 0x0040,
+ EXYNOS5_GPF1 = EXYNOS5420_GPIO_PART4_BASE + 0x0060,
+
+ EXYNOS5_GPG0 = EXYNOS5420_GPIO_PART4_BASE + 0x0080,
+ EXYNOS5_GPG1 = EXYNOS5420_GPIO_PART4_BASE + 0x00a0,
+ EXYNOS5_GPG2 = EXYNOS5420_GPIO_PART4_BASE + 0x00c0,
+
+ EXYNOS5_GPJ4 = EXYNOS5420_GPIO_PART4_BASE + 0x00e0,
+
+ /* base == EXYNOS5420_GPIO_PART5_BASE */
+ EXYNOS5_GPA0 = EXYNOS5420_GPIO_PART5_BASE + 0x0000,
+ EXYNOS5_GPA1 = EXYNOS5420_GPIO_PART5_BASE + 0x0020,
+ EXYNOS5_GPA2 = EXYNOS5420_GPIO_PART5_BASE + 0x0040,
+
+ EXYNOS5_GPB0 = EXYNOS5420_GPIO_PART5_BASE + 0x0060,
+ EXYNOS5_GPB1 = EXYNOS5420_GPIO_PART5_BASE + 0x0080,
+ EXYNOS5_GPB2 = EXYNOS5420_GPIO_PART5_BASE + 0x00a0,
+ EXYNOS5_GPB3 = EXYNOS5420_GPIO_PART5_BASE + 0x00c0,
+ EXYNOS5_GPB4 = EXYNOS5420_GPIO_PART5_BASE + 0x00e0,
+
+ EXYNOS5_GPH0 = EXYNOS5420_GPIO_PART5_BASE + 0x0100,
+
+ /* base == EXYNOS5420_GPIO_PART6_BASE */
+ EXYNOS5_GPZ0 = EXYNOS5420_GPIO_PART6_BASE + 0x0000,
+};
+
+enum {
+ /* GPIO banks are split into this many parts */
+ EXYNOS_GPIO_NUM_PARTS = 6
+};
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos5_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ GPIO_Y70,
+ GPIO_Y71,
+ GPIO_Y72,
+ GPIO_Y73,
+ GPIO_Y74,
+ GPIO_Y75,
+ GPIO_Y76,
+ GPIO_Y77,
+
+ /* GPIO_PART2_STARTS */
+ GPIO_MAX_PORT_PART_1,
+ GPIO_X00 = GPIO_MAX_PORT_PART_1, /* 0x08 */
+ GPIO_X01,
+ GPIO_X02,
+ GPIO_X03,
+ GPIO_X04,
+ GPIO_X05,
+ GPIO_X06,
+ GPIO_X07,
+ GPIO_X10,
+ GPIO_X11,
+ GPIO_X12,
+ GPIO_X13,
+ GPIO_X14,
+ GPIO_X15,
+ GPIO_X16,
+ GPIO_X17,
+ GPIO_X20,
+ GPIO_X21,
+ GPIO_X22,
+ GPIO_X23,
+ GPIO_X24,
+ GPIO_X25,
+ GPIO_X26,
+ GPIO_X27,
+ GPIO_X30,
+ GPIO_X31,
+ GPIO_X32,
+ GPIO_X33,
+ GPIO_X34,
+ GPIO_X35,
+ GPIO_X36,
+ GPIO_X37,
+
+ /* GPIO_PART3_STARTS */
+ GPIO_MAX_PORT_PART_2,
+ GPIO_C00 = GPIO_MAX_PORT_PART_2, /* 0x28 */
+ GPIO_C01,
+ GPIO_C02,
+ GPIO_C03,
+ GPIO_C04,
+ GPIO_C05,
+ GPIO_C06,
+ GPIO_C07,
+ GPIO_C10,
+ GPIO_C11,
+ GPIO_C12,
+ GPIO_C13,
+ GPIO_C14,
+ GPIO_C15,
+ GPIO_C16,
+ GPIO_C17,
+ GPIO_C20,
+ GPIO_C21,
+ GPIO_C22,
+ GPIO_C23,
+ GPIO_C24,
+ GPIO_C25,
+ GPIO_C26,
+ GPIO_C27,
+ GPIO_C30,
+ GPIO_C31,
+ GPIO_C32,
+ GPIO_C33,
+ GPIO_C34,
+ GPIO_C35,
+ GPIO_C36,
+ GPIO_C37,
+ GPIO_C40,
+ GPIO_C41,
+ GPIO_C42,
+ GPIO_C43,
+ GPIO_C44,
+ GPIO_C45,
+ GPIO_C46,
+ GPIO_C47,
+
+ GPIO_D10, /* 0x50 */
+ GPIO_D11,
+ GPIO_D12,
+ GPIO_D13,
+ GPIO_D14,
+ GPIO_D15,
+ GPIO_D16,
+ GPIO_D17,
+
+ GPIO_Y00, /* 0x58 */
+ GPIO_Y01,
+ GPIO_Y02,
+ GPIO_Y03,
+ GPIO_Y04,
+ GPIO_Y05,
+ GPIO_Y06,
+ GPIO_Y07,
+ GPIO_Y10,
+ GPIO_Y11,
+ GPIO_Y12,
+ GPIO_Y13,
+ GPIO_Y14,
+ GPIO_Y15,
+ GPIO_Y16,
+ GPIO_Y17,
+ GPIO_Y20,
+ GPIO_Y21,
+ GPIO_Y22,
+ GPIO_Y23,
+ GPIO_Y24,
+ GPIO_Y25,
+ GPIO_Y26,
+ GPIO_Y27,
+ GPIO_Y30,
+ GPIO_Y31,
+ GPIO_Y32,
+ GPIO_Y33,
+ GPIO_Y34,
+ GPIO_Y35,
+ GPIO_Y36,
+ GPIO_Y37,
+ GPIO_Y40,
+ GPIO_Y41,
+ GPIO_Y42,
+ GPIO_Y43,
+ GPIO_Y44,
+ GPIO_Y45,
+ GPIO_Y46,
+ GPIO_Y47,
+ GPIO_Y50,
+ GPIO_Y51,
+ GPIO_Y52,
+ GPIO_Y53,
+ GPIO_Y54,
+ GPIO_Y55,
+ GPIO_Y56,
+ GPIO_Y57,
+ GPIO_Y60,
+ GPIO_Y61,
+ GPIO_Y62,
+ GPIO_Y63,
+ GPIO_Y64,
+ GPIO_Y65,
+ GPIO_Y66,
+ GPIO_Y67,
+
+ /* GPIO_PART4_STARTS */
+ GPIO_MAX_PORT_PART_3,
+ GPIO_E00 = GPIO_MAX_PORT_PART_3, /* 0x90 */
+ GPIO_E01,
+ GPIO_E02,
+ GPIO_E03,
+ GPIO_E04,
+ GPIO_E05,
+ GPIO_E06,
+ GPIO_E07,
+ GPIO_E10,
+ GPIO_E11,
+ GPIO_E12,
+ GPIO_E13,
+ GPIO_E14,
+ GPIO_E15,
+ GPIO_E16,
+ GPIO_E17,
+
+ GPIO_F00, /* 0xa0 */
+ GPIO_F01,
+ GPIO_F02,
+ GPIO_F03,
+ GPIO_F04,
+ GPIO_F05,
+ GPIO_F06,
+ GPIO_F07,
+ GPIO_F10,
+ GPIO_F11,
+ GPIO_F12,
+ GPIO_F13,
+ GPIO_F14,
+ GPIO_F15,
+ GPIO_F16,
+ GPIO_F17,
+
+ GPIO_G00, /* 0xb0 */
+ GPIO_G01,
+ GPIO_G02,
+ GPIO_G03,
+ GPIO_G04,
+ GPIO_G05,
+ GPIO_G06,
+ GPIO_G07,
+ GPIO_G10,
+ GPIO_G11,
+ GPIO_G12,
+ GPIO_G13,
+ GPIO_G14,
+ GPIO_G15,
+ GPIO_G16,
+ GPIO_G17,
+ GPIO_G20,
+ GPIO_G21,
+ GPIO_G22,
+ GPIO_G23,
+ GPIO_G24,
+ GPIO_G25,
+ GPIO_G26,
+ GPIO_G27,
+
+ GPIO_J40, /* 0xc8 */
+ GPIO_J41,
+ GPIO_J42,
+ GPIO_J43,
+ GPIO_J44,
+ GPIO_J45,
+ GPIO_J46,
+ GPIO_J47,
+
+ /* GPIO_PART5_STARTS */
+ GPIO_MAX_PORT_PART_4,
+ GPIO_A00 = GPIO_MAX_PORT_PART_4, /* 0xd0 */
+ GPIO_A01,
+ GPIO_A02,
+ GPIO_A03,
+ GPIO_A04,
+ GPIO_A05,
+ GPIO_A06,
+ GPIO_A07,
+ GPIO_A10,
+ GPIO_A11,
+ GPIO_A12,
+ GPIO_A13,
+ GPIO_A14,
+ GPIO_A15,
+ GPIO_A16,
+ GPIO_A17,
+ GPIO_A20,
+ GPIO_A21,
+ GPIO_A22,
+ GPIO_A23,
+ GPIO_A24,
+ GPIO_A25,
+ GPIO_A26,
+ GPIO_A27,
+
+ GPIO_B00, /* 0xe8 */
+ GPIO_B01,
+ GPIO_B02,
+ GPIO_B03,
+ GPIO_B04,
+ GPIO_B05,
+ GPIO_B06,
+ GPIO_B07,
+ GPIO_B10,
+ GPIO_B11,
+ GPIO_B12,
+ GPIO_B13,
+ GPIO_B14,
+ GPIO_B15,
+ GPIO_B16,
+ GPIO_B17,
+ GPIO_B20,
+ GPIO_B21,
+ GPIO_B22,
+ GPIO_B23,
+ GPIO_B24,
+ GPIO_B25,
+ GPIO_B26,
+ GPIO_B27,
+ GPIO_B30,
+ GPIO_B31,
+ GPIO_B32,
+ GPIO_B33,
+ GPIO_B34,
+ GPIO_B35,
+ GPIO_B36,
+ GPIO_B37,
+ GPIO_B40,
+ GPIO_B41,
+ GPIO_B42,
+ GPIO_B43,
+ GPIO_B44,
+ GPIO_B45,
+ GPIO_B46,
+ GPIO_B47,
+
+ GPIO_H00, /* 0x110 */
+ GPIO_H01,
+ GPIO_H02,
+ GPIO_H03,
+ GPIO_H04,
+ GPIO_H05,
+ GPIO_H06,
+ GPIO_H07,
+
+ /* GPIO_PART6_STARTS */
+ GPIO_MAX_PORT_PART_5,
+ GPIO_Z00 = GPIO_MAX_PORT_PART_5, /* 0x118 */
+ GPIO_Z01,
+ GPIO_Z02,
+ GPIO_Z03,
+ GPIO_Z04,
+ GPIO_Z05,
+ GPIO_Z06,
+ GPIO_Z07,
+ GPIO_MAX_PORT
+};
+
+/**
+ * Set GPIO pin configuration.
+ *
+ * @param gpio GPIO pin
+ * @param cfg Either GPIO_INPUT, GPIO_OUTPUT, or GPIO_IRQ
+ */
+void gpio_cfg_pin(int gpio, int cfg);
+
+/**
+ * Set GPIO pull mode.
+ *
+ * @param gpio GPIO pin
+ * @param mode Either GPIO_PULL_DOWN or GPIO_PULL_UP
+ */
+void gpio_set_pull(int gpio, int mode);
+
+/**
+ * Set GPIO drive strength level.
+ *
+ * @param gpio GPIO pin
+ * @param mode Either GPIO_DRV_1X, GPIO_DRV_2X, GPIO_DRV_3X, or GPIO_DRV_4X
+ */
+void gpio_set_drv(int gpio, int mode);
+
+/**
+ * Set GPIO drive rate.
+ *
+ * @param gpio GPIO pin
+ * @param mode Either GPIO_DRV_FAST or GPIO_DRV_SLOW
+ */
+void gpio_set_rate(int gpio, int mode);
+
+/*
+ * reads only a single GPIO
+ *
+ * @param gpio GPIO to read
+ * @return -1 if the value cannot be determined. Otherwise returns
+ * the corresponding MVL3 enum value.
+ */
+int gpio_read_mvl3(unsigned gpio);
+
+void gpio_info(void);
+
+/*
+ * Generic GPIO API for U-Boot
+ *
+ * GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
+ * by the SOC/architecture.
+ *
+ * Each GPIO can be an input or output. If an input then its value can
+ * be read as 0 or 1. If an output then its value can be set to 0 or 1.
+ * If you try to write an input then the value is undefined. If you try
+ * to read an output, barring something very unusual, you will get
+ * back the value of the output that you previously set.
+ *
+ * In some cases the operation may fail, for example if the GPIO number
+ * is out of range, or the GPIO is not available because its pin is
+ * being used by another function. In that case, functions may return
+ * an error value of -1.
+ */
+
+/**
+ * Make a GPIO an input.
+ *
+ * @param gpio GPIO number
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_input(unsigned gpio);
+
+/**
+ * Make a GPIO an output, and set its value.
+ *
+ * @param gpio GPIO number
+ * @param value GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_output(unsigned gpio, int value);
+
+/**
+ * Get a GPIO's value. This will work whether the GPIO is an input
+ * or an output.
+ *
+ * @param gpio GPIO number
+ * @return 0 if low, 1 if high, -1 on error
+ */
+int gpio_get_value(unsigned gpio);
+
+/**
+ * Set an output GPIO's value. The GPIO must already be an output or
+ * this function may have no effect.
+ *
+ * @param gpio GPIO number
+ * @param value GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_set_value(unsigned gpio, int value);
+
+/*
+ * Many-value logic (3 states). This can be used for inputs whereby presence
+ * of external pull-up or pull-down resistors can be added to overcome internal
+ * pull-ups/pull-downs and force a single value.
+ *
+ * Thus, external pull resistors can force a 0 or 1 and if the value changes
+ * along with internal pull-up/down enable then the input is floating.
+ *
+ * Vpd | Vpu | MVL
+ * -----------------
+ * 0 | 0 | 0
+ * -----------------
+ * 0 | 1 | Z <-- floating input will follow internal pull up/down
+ * -----------------
+ * 1 | 1 | 1
+ */
+enum mvl3 {
+ LOGIC_0,
+ LOGIC_1,
+ LOGIC_Z, /* high impedance / tri-stated / floating */
+};
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_GPIO_H */
diff --git a/src/soc/samsung/exynos5420/include/soc/i2c.h b/src/soc/samsung/exynos5420/include/soc/i2c.h
new file mode 100644
index 0000000000..b9e3c0f5eb
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/i2c.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_I2C_H
+#define CPU_SAMSUNG_EXYNOS5420_I2C_H
+
+void i2c_init(unsigned bus, int speed, int slaveadd);
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_I2C_H */
diff --git a/src/soc/samsung/exynos5420/include/soc/i2s-regs.h b/src/soc/samsung/exynos5420/include/soc/i2s-regs.h
new file mode 100644
index 0000000000..28d2685c63
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/i2s-regs.h
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Taken from the kernel code */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H
+#define CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H
+
+#define I2SCON 0x0
+#define I2SMOD 0x4
+#define I2SFIC 0x8
+#define I2SPSR 0xc
+#define I2STXD 0x10
+#define I2SRXD 0x14
+#define I2SFICS 0x18
+#define I2STXDS 0x1c
+#define I2SAHB 0x20
+#define I2SSTR0 0x24
+#define I2SSIZE 0x28
+#define I2STRNCNT 0x2c
+#define I2SLVL0ADDR 0x30
+#define I2SLVL1ADDR 0x34
+#define I2SLVL2ADDR 0x38
+#define I2SLVL3ADDR 0x3c
+
+#define CON_RSTCLR (1 << 31)
+#define CON_FRXOFSTATUS (1 << 26)
+#define CON_FRXORINTEN (1 << 25)
+#define CON_FTXSURSTAT (1 << 24)
+#define CON_FTXSURINTEN (1 << 23)
+#define CON_TXSDMA_PAUSE (1 << 20)
+#define CON_TXSDMA_ACTIVE (1 << 18)
+
+#define CON_FTXURSTATUS (1 << 17)
+#define CON_FTXURINTEN (1 << 16)
+#define CON_TXFIFO2_EMPTY (1 << 15)
+#define CON_TXFIFO1_EMPTY (1 << 14)
+#define CON_TXFIFO2_FULL (1 << 13)
+#define CON_TXFIFO1_FULL (1 << 12)
+
+#define CON_LRINDEX (1 << 11)
+#define CON_TXFIFO_EMPTY (1 << 10)
+#define CON_RXFIFO_EMPTY (1 << 9)
+#define CON_TXFIFO_FULL (1 << 8)
+#define CON_RXFIFO_FULL (1 << 7)
+#define CON_TXDMA_PAUSE (1 << 6)
+#define CON_RXDMA_PAUSE (1 << 5)
+#define CON_TXCH_PAUSE (1 << 4)
+#define CON_RXCH_PAUSE (1 << 3)
+#define CON_TXDMA_ACTIVE (1 << 2)
+#define CON_RXDMA_ACTIVE (1 << 1)
+#define CON_ACTIVE (1 << 0)
+
+#define MOD_OPCLK_CDCLK_OUT (0 << 30)
+#define MOD_OPCLK_CDCLK_IN (1 << 30)
+#define MOD_OPCLK_BCLK_OUT (2 << 30)
+#define MOD_OPCLK_PCLK (3 << 30)
+#define MOD_OPCLK_MASK (3 << 30)
+#define MOD_TXS_IDMA (1 << 28) /* Sec_TXFIFO use I-DMA */
+
+#define MOD_BLCS_SHIFT 26
+#define MOD_BLCS_16BIT (0 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_8BIT (1 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_24BIT (2 << MOD_BLCS_SHIFT)
+#define MOD_BLCS_MASK (3 << MOD_BLCS_SHIFT)
+
+#define MOD_BLCP_SHIFT 24
+#define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT)
+
+#define MOD_C2DD_HHALF (1 << 21) /* Discard Higher-half */
+#define MOD_C2DD_LHALF (1 << 20) /* Discard Lower-half */
+#define MOD_C1DD_HHALF (1 << 19)
+#define MOD_C1DD_LHALF (1 << 18)
+#define MOD_DC2_EN (1 << 17)
+#define MOD_DC1_EN (1 << 16)
+#define MOD_BLC_16BIT (0 << 13)
+#define MOD_BLC_8BIT (1 << 13)
+#define MOD_BLC_24BIT (2 << 13)
+#define MOD_BLC_MASK (3 << 13)
+
+#define MOD_IMS_SYSMUX (1 << 10)
+#define MOD_SLAVE (1 << 11)
+#define MOD_TXONLY (0 << 8)
+#define MOD_RXONLY (1 << 8)
+#define MOD_TXRX (2 << 8)
+#define MOD_MASK (3 << 8)
+#define MOD_LR_LLOW (0 << 7)
+#define MOD_LR_RLOW (1 << 7)
+#define MOD_SDF_IIS (0 << 5)
+#define MOD_SDF_MSB (1 << 5)
+#define MOD_SDF_LSB (2 << 5)
+#define MOD_SDF_MASK (3 << 5)
+#define MOD_RCLK_256FS (0 << 3)
+#define MOD_RCLK_512FS (1 << 3)
+#define MOD_RCLK_384FS (2 << 3)
+#define MOD_RCLK_768FS (3 << 3)
+#define MOD_RCLK_MASK (3 << 3)
+#define MOD_BCLK_32FS (0 << 1)
+#define MOD_BCLK_48FS (1 << 1)
+#define MOD_BCLK_16FS (2 << 1)
+#define MOD_BCLK_24FS (3 << 1)
+#define MOD_BCLK_MASK (3 << 1)
+#define MOD_8BIT (1 << 0)
+
+#define MOD_CDCLKCON (1 << 12)
+
+#define PSR_PSREN (1 << 15)
+
+#define FIC_TXFLUSH (1 << 15)
+#define FIC_RXFLUSH (1 << 7)
+
+#define AHB_INTENLVL0 (1 << 24)
+#define AHB_LVL0INT (1 << 20)
+#define AHB_CLRLVL0INT (1 << 16)
+#define AHB_DMARLD (1 << 5)
+#define AHB_INTMASK (1 << 3)
+#define AHB_DMAEN (1 << 0)
+#define AHB_LVLINTMASK (0xf << 20)
+
+#define I2SSIZE_TRNMSK (0xffff)
+#define I2SSIZE_SHIFT (16)
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_I2S_REGS_H */
diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld
new file mode 100644
index 0000000000..3259ff907b
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * Note: The BootROM loads the 8K BL1 at [0x2020000:0x2022000), so the bootblock
+ * must be placed after that. After the handoff, the space can be reclaimed.
+ */
+
+SECTIONS
+{
+ SRAM_START(0x2020000)
+ /* 17K hole, includes BL1 */
+ /* Bootblock is preceeded by 16 byte variable length BL2 checksum. */
+ BOOTBLOCK(0x2024410, 32K - 16)
+ /* 15K hole */
+ ROMSTAGE(0x2030000, 128K)
+ /* 32K hole */
+ TTB(0x2058000, 16K)
+ PRERAM_CBFS_CACHE(0x205C000, 76K)
+ STACK(0x206F000, 16K)
+ /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
+ * seem to be implemented right now? */
+ SRAM_END(0x2074000)
+
+ DRAM_START(0x20000000)
+ RAMSTAGE(0x20000000, 128K)
+ POSTRAM_CBFS_CACHE(0x21000000, 8M)
+ DMA_COHERENT(0x77300000, 1M)
+}
diff --git a/src/soc/samsung/exynos5420/include/soc/periph.h b/src/soc/samsung/exynos5420/include/soc/periph.h
new file mode 100644
index 0000000000..94f150e6dd
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/periph.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_PERIPH_H
+#define CPU_SAMSUNG_EXYNOS5420_PERIPH_H
+
+/*
+ * Peripherals requiring clock/pinmux configuration. List will
+ * grow with support for more devices getting added.
+ *
+ * At present the order is arbitrary - we may be able to take advantage
+ * of some orthogonality later.
+ */
+enum periph_id {
+ PERIPH_ID_UART0,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_SDMMC0,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SDMMC3,
+
+ PERIPH_ID_SROMC = 9,
+ PERIPH_ID_SPI0,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_SPI3,
+ PERIPH_ID_SPI4,
+ PERIPH_ID_LCD,
+ PERIPH_ID_BACKLIGHT,
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_I2C8,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2C10,
+ PERIPH_ID_DPHPD, /* eDP hot plug detect */
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_SATA,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/pinmux.h b/src/soc/samsung/exynos5420/include/soc/pinmux.h
new file mode 100644
index 0000000000..fc09fc95fb
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/pinmux.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_PINMUX_H
+#define CPU_SAMSUNG_EXYNOS5420_PINMUX_H
+
+void exynos_pinmux_uart0(void);
+void exynos_pinmux_uart1(void);
+void exynos_pinmux_uart2(void);
+void exynos_pinmux_uart3(void);
+
+void exynos_pinmux_sdmmc0(void);
+void exynos_pinmux_sdmmc1(void);
+void exynos_pinmux_sdmmc2(void);
+void exynos_pinmux_sdmmc3(void);
+
+void exynos_pinmux_spi0(void);
+void exynos_pinmux_spi1(void);
+void exynos_pinmux_spi2(void);
+void exynos_pinmux_spi3(void);
+void exynos_pinmux_spi4(void);
+
+void exynos_pinmux_i2c0(void);
+void exynos_pinmux_i2c1(void);
+void exynos_pinmux_i2c2(void);
+void exynos_pinmux_i2c3(void);
+void exynos_pinmux_i2c4(void);
+void exynos_pinmux_i2c5(void);
+void exynos_pinmux_i2c6(void);
+void exynos_pinmux_i2c7(void);
+void exynos_pinmux_i2c8(void);
+void exynos_pinmux_i2c9(void);
+void exynos_pinmux_i2c10(void);
+
+void exynos_pinmux_dphpd(void);
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/power.h b/src/soc/samsung/exynos5420/include/soc/power.h
new file mode 100644
index 0000000000..0d31dc440b
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/power.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Register map for Exynos5 PMU */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_POWER_H
+#define CPU_SAMSUNG_EXYNOS5420_POWER_H
+
+#include <soc/cpu.h>
+
+/* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
+void power_enable_hw_thermal_trip(void);
+
+#define MIPI_PHY1_CONTROL_ENABLE (1 << 0)
+#define MIPI_PHY1_CONTROL_M_RESETN (1 << 2)
+
+#define POWER_USB_PHY_CTRL_EN (1 << 0)
+#define POWER_PS_HOLD_CONTROL_DATA_HIGH (1 << 8)
+#define POWER_ENABLE_HW_TRIP (1UL << 31)
+
+#define EXYNOS_DP_PHY_ENABLE (1 << 0)
+
+/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */
+#define PMU_DEBUG_XXTI 0x1000
+/* Mask bit[12:8] for xxti clock selection */
+#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00
+
+/* Power Management Unit register map */
+struct exynos5_power {
+ /* Add registers as and when required */
+ uint32_t om_stat; /* 0x0000 */
+ uint8_t reserved1[0x03fc];
+ uint32_t sw_reset; /* 0x0400 */
+ uint8_t reserved2[0x0300];
+ uint32_t usb_drd0_phy_ctrl; /* 0x0704 */
+ uint32_t usb_drd1_phy_ctrl; /* 0x0708 */
+ uint32_t usb_host_phy_ctrl; /* 0x070c */
+ uint8_t reserved3[0x4];
+ uint32_t mipi_phy1_control; /* 0x0714 */
+ uint8_t reserved4[0x8];
+ uint32_t dptx_phy_control; /* 0x0720 */
+ uint8_t reserved5[0xdc];
+ uint32_t inform0; /* 0x0800 */
+ uint32_t inform1; /* 0x0804 */
+ uint8_t reserved6[0x0f8];
+ uint32_t spare0; /* 0x0900 */
+ uint8_t reserved7[0x0fc];
+ uint32_t pmu_debug; /* 0x0a00 */
+ uint8_t reserved8[0x15fc];
+ struct { /* 0x2000 */
+ uint32_t config; /* 0x00 */
+ uint32_t status; /* 0x04 */
+ uint8_t reserved[0x78];
+ } arm_core[4];
+ uint8_t reserved9[0xe04];
+ uint32_t padret_dram_status; /* 0x3004 */
+ uint8_t reservedA[0xe0];
+ uint32_t padret_uart_opt; /* 0x30e8 */
+ uint8_t reservedB[0xfc];
+ uint32_t padret_dram_cblk_opt; /* 0x31e8 */
+ uint8_t reservedC[0x120];
+ uint32_t ps_hold_ctrl; /* 0x330c */
+} __attribute__ ((__packed__));
+check_member(exynos5_power, ps_hold_ctrl, 0x330c);
+
+static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;
+
+/**
+ * Perform a software reset.
+ */
+void power_reset(void);
+
+/**
+ * Power off the system; it should never return.
+ */
+void power_shutdown(void);
+
+/* Enable DPTX PHY */
+void power_enable_dp_phy(void);
+
+/* Initialize the pmic voltages to power up the system */
+int power_init(void);
+
+/* Read the reset status. */
+uint32_t power_read_reset_status(void);
+
+/* Read the resume function and call it. */
+void power_exit_wakeup(void);
+
+/* pmu debug is used for xclkout, enable xclkout with source as XXTI */
+void power_enable_xclkout(void);
+
+/* Release UART retention on resume (only for debugging, may conflict with
+ * kernel). */
+void power_release_uart_retention(void);
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/setup.h b/src/soc/samsung/exynos5420/include/soc/setup.h
new file mode 100644
index 0000000000..e7b5bd2e08
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/setup.h
@@ -0,0 +1,886 @@
+ /*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Machine Specific Values for SMDK5420 board based on Exynos5 */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_SETUP_H
+#define CPU_SAMSUNG_EXYNOS5420_SETUP_H
+
+struct exynos5_dmc;
+enum ddr_mode;
+struct exynos5_phy_control;
+
+#define NOT_AVAILABLE 0
+#define DATA_MASK 0xFFFFF
+
+#define ENABLE_BIT 0x1
+#define DISABLE_BIT 0x0
+#define CA_SWAP_EN (1 << 0)
+
+/* TZPC : Register Offsets */
+#define TZPC0_BASE 0x10100000
+#define TZPC1_BASE 0x10110000
+#define TZPC2_BASE 0x10120000
+#define TZPC3_BASE 0x10130000
+#define TZPC4_BASE 0x10140000
+#define TZPC5_BASE 0x10150000
+#define TZPC6_BASE 0x10160000
+#define TZPC7_BASE 0x10170000
+#define TZPC8_BASE 0x10180000
+#define TZPC9_BASE 0x10190000
+
+#define APLL_FOUT (1 << 0)
+#define KPLL_FOUT (1 << 0)
+
+#define CLK_DIV_CPERI1_VAL 0x3f3f0000
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x0020f300)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x0020f300)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL (0x0020f300)
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL (0x0020f300)
+
+/* GPLL_CON1 */
+#define GPLL_CON1_VAL (NOT_AVAILABLE)
+
+/* EPLL_CON1, CON2 */
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
+
+/* VPLL_CON1, CON2 */
+#define VPLL_CON1_VAL 0x0020f300
+#define VPLL_CON2_VAL NOT_AVAILABLE
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL 0x00000000
+#define RPLL_CON2_VAL 0x00000080
+
+/* BPLL_CON1 */
+#define BPLL_CON1_VAL 0x0020f300
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL 0x0020f300
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL 0x00000080
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL 0x200000
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 1
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
+/* MEMCONTROL register bit fields */
+#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
+#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
+#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
+#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
+#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
+#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
+
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
+#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
+
+#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
+
+#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
+#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
+
+#define DMC_MEMCONTROL_BL_8 (3 << 20)
+#define DMC_MEMCONTROL_BL_4 (2 << 20)
+
+#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
+
+#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
+#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
+
+/* MEMCONFIG0 register bit fields */
+#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12)
+#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
+#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
+#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4)
+#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
+
+#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
+#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
+
+#define DMC_PRECHCONFIG_VAL 0xFF000000
+#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
+
+#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
+#define DFI_INIT_START (1 << 28)
+#define EMPTY (1 << 8)
+#define AREF_EN (1 << 5)
+
+#define DFI_INIT_COMPLETE_CHO (1 << 2)
+#define DFI_INIT_COMPLETE_CH1 (1 << 3)
+
+#define RDLVL_COMPLETE_CHO (1 << 14)
+#define RDLVL_COMPLETE_CH1 (1 << 15)
+
+#define CLK_STOP_EN (1 << 0)
+#define DPWRDN_EN (1 << 1)
+#define DSREF_EN (1 << 5)
+
+/* COJCONTROL register bit fields */
+#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
+#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
+#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
+#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
+#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
+
+/* CLK_FSYS */
+#define CLK_SRC_FSYS0_VAL 0x33033300
+#define CLK_DIV_FSYS0_VAL 0x0
+#define CLK_DIV_FSYS1_VAL 0x04f13c4f
+#define CLK_DIV_FSYS2_VAL 0x041d0000
+
+#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x2
+#define COPY_RATIO 0x0
+
+/* CLK_DIV_CPU1 = 0x00000003 */
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
+ | (COPY_RATIO))
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL 0x00000000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL 0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL 0x00120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL 0x07070700
+
+/* CLK_DIV_SYSRGT */
+#define CLK_DIV_SYSRGT_VAL 0x00000111
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL 0x12
+
+/* CLK_DIV_SYSLFT */
+#define CLK_DIV_SYSLFT_VAL 0x00000311
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL 0x00000001
+#define MUX_MCLK_CDR_MSPLL (1 << 4)
+#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
+#define BPLL_SEL_MASK 0x7
+#define FOUTBPLL 2
+
+/* CLK_DIV_CDREX */
+#define CLK_DIV_CDREX0_VAL 0x30010100
+#define CLK_DIV_CDREX1_VAL 0x300
+
+#define CLK_DIV_CDREX_VAL 0x17010100
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL 0x01440020
+
+/* CLK_SRC_TOP */
+#define CLK_SRC_TOP0_VAL 0x11101102
+#define CLK_SRC_TOP1_VAL 0x00200000
+#define CLK_SRC_TOP2_VAL 0x11101010
+#define CLK_SRC_TOP3_VAL 0x11111111
+#define CLK_SRC_TOP4_VAL 0x11110111
+#define CLK_SRC_TOP5_VAL 0x11111111
+#define CLK_SRC_TOP6_VAL 0x11110111
+#define CLK_SRC_TOP7_VAL 0x00022200
+
+/* CLK_DIV_TOP */
+#define CLK_DIV_TOP0_VAL 0x22512211
+#define CLK_DIV_TOP1_VAL 0x13200900
+#define CLK_DIV_TOP2_VAL 0x11101110
+
+/* APLL_LOCK */
+#define APLL_LOCK_VAL (0x320)
+/* MPLL_LOCK */
+#define MPLL_LOCK_VAL (0x258)
+/* BPLL_LOCK */
+#define BPLL_LOCK_VAL (0x258)
+/* CPLL_LOCK */
+#define CPLL_LOCK_VAL (0x190)
+/* DPLL_LOCK */
+#define DPLL_LOCK_VAL (0x190)
+/* GPLL_LOCK */
+#define GPLL_LOCK_VAL NOT_AVAILABLE
+/* IPLL_LOCK */
+#define IPLL_LOCK_VAL (0x320)
+/* KPLL_LOCK */
+#define KPLL_LOCK_VAL (0x258)
+/* SPLL_LOCK */
+#define SPLL_LOCK_VAL (0x320)
+/* RPLL_LOCK */
+#define RPLL_LOCK_VAL (0x2328)
+/* EPLL_LOCK */
+#define EPLL_LOCK_VAL (0x2328)
+/* VPLL_LOCK */
+#define VPLL_LOCK_VAL (0x258)
+
+#define MUX_APLL_SEL_MASK (1 << 0)
+#define MUX_MPLL_SEL_MASK (1 << 8)
+#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
+#define MUX_CPLL_SEL_MASK (1 << 8)
+#define MUX_EPLL_SEL_MASK (1 << 12)
+#define MUX_VPLL_SEL_MASK (1 << 16)
+#define MUX_GPLL_SEL_MASK (1 << 28)
+#define MUX_BPLL_SEL_MASK (1 << 0)
+#define MUX_HPM_SEL_MASK (1 << 20)
+#define HPM_SEL_SCLK_MPLL (1 << 21)
+#define PLL_LOCKED (1 << 29)
+#define APLL_CON0_LOCKED (1 << 29)
+#define MPLL_CON0_LOCKED (1 << 29)
+#define BPLL_CON0_LOCKED (1 << 29)
+#define CPLL_CON0_LOCKED (1 << 29)
+#define EPLL_CON0_LOCKED (1 << 29)
+#define GPLL_CON0_LOCKED (1 << 29)
+#define VPLL_CON0_LOCKED (1 << 29)
+#define CLK_REG_DISABLE 0x0
+#define TOP2_VAL 0x0110000
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+/* CLK_SRC_KFC */
+#define SRC_KFC_HPM_SEL (1 << 15)
+
+/* CLK_SRC_KFC */
+#define CLK_SRC_KFC_VAL 0x00008001
+
+/* CLK_DIV_KFC */
+#define CLK_DIV_KFC_VAL 0x03300110
+
+/* CLK_DIV2_RATIO */
+#define CLK_DIV2_RATIO 0x10111150
+
+/* CLK_DIV4_RATIO */
+#define CLK_DIV4_RATIO 0x00000003
+
+/* CLK_DIV_G2D */
+#define CLK_DIV_G2D 0x00000010
+
+/* CLK_SRC_PERIC0 */
+#define SPDIF_SEL 1
+#define PWM_SEL 3
+#define UART4_SEL 3
+#define UART3_SEL 3
+#define UART2_SEL 3
+#define UART1_SEL 3
+#define UART0_SEL 3
+/* SRC_CLOCK = SCLK_RPLL */
+#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
+ | (PWM_SEL << 24) \
+ | (UART4_SEL << 20) \
+ | (UART3_SEL << 16) \
+ | (UART2_SEL << 12) \
+ | (UART1_SEL << 8) \
+ | (UART0_SEL << 4))
+
+/* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define SPI0_SEL 3
+#define SPI1_SEL 3
+#define SPI2_SEL 3
+/* SRC_CLOCK = SCLK_EPLL */
+#define AUDIO0_SEL 6
+#define AUDIO1_SEL 6
+#define AUDIO2_SEL 6
+#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
+ | (SPI1_SEL << 24) \
+ | (SPI0_SEL << 20) \
+ | (AUDIO2_SEL << 16) \
+ | (AUDIO2_SEL << 12) \
+ | (AUDIO2_SEL << 8))
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL 0x33366000
+#define CLK_DIV_ISP0_VAL 0x13131300
+#define CLK_DIV_ISP1_VAL 0xbb110202
+
+/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
+#define SPI0_ISP_RATIO 0xf
+#define SPI1_ISP_RATIO 0xf
+#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
+ | (SPI0_ISP_RATIO << 0)
+
+/* CLK_DIV_PERIL0 */
+#define PWM_RATIO 8
+#define UART4_RATIO 9
+#define UART3_RATIO 9
+#define UART2_RATIO 9
+#define UART1_RATIO 9
+#define UART0_RATIO 9
+
+#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
+ | (UART4_RATIO << 24) \
+ | (UART3_RATIO << 20) \
+ | (UART2_RATIO << 16) \
+ | (UART1_RATIO << 12) \
+ | (UART0_RATIO << 8))
+
+/* CLK_DIV_PERIC1 */
+#define SPI2_RATIO 0x1
+#define SPI1_RATIO 0x1
+#define SPI0_RATIO 0x1
+#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
+ | (SPI1_RATIO << 24) \
+ | (SPI0_RATIO << 20))
+
+/* CLK_DIV_PERIC2 */
+#define PCM2_RATIO 0x3
+#define PCM1_RATIO 0x3
+#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
+ | (PCM1_RATIO << 16))
+
+/* CLK_DIV_PERIC3 */
+#define AUDIO2_RATIO 0x5
+#define AUDIO1_RATIO 0x5
+#define AUDIO0_RATIO 0x5
+#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
+ | (AUDIO1_RATIO << 24) \
+ | (AUDIO0_RATIO << 20))
+
+/* CLK_DIV_PERIC4 */
+#define SPI2_PRE_RATIO 0x3
+#define SPI1_PRE_RATIO 0x3
+#define SPI0_PRE_RATIO 0x3
+#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
+ | (SPI1_PRE_RATIO << 16) \
+ | (SPI0_PRE_RATIO << 8))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO_MASK 0xf
+#define MMC2_RATIO_VAL 0x3
+#define MMC2_RATIO_OFFSET 0
+
+#define MMC2_PRE_RATIO_MASK 0xff
+#define MMC2_PRE_RATIO_VAL 0x9
+#define MMC2_PRE_RATIO_OFFSET 8
+
+#define MMC3_RATIO_MASK 0xf
+#define MMC3_RATIO_VAL 0x1
+#define MMC3_RATIO_OFFSET 16
+
+#define MMC3_PRE_RATIO_MASK 0xff
+#define MMC3_PRE_RATIO_VAL 0x0
+#define MMC3_PRE_RATIO_OFFSET 24
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+/* CLK_SRC_DISP1_0 */
+#define CLK_SRC_DISP1_0_VAL 0x10006000
+#define CLK_DIV_DISP1_0_VAL 0x01050210
+
+/*
+ * DIV_DISP1_0
+ * For DP, divisor should be 2
+ */
+#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_GATE_DP1_ALLOW (1 << 4)
+
+/* CLK_GATE_IP_SYSRGT */
+#define CLK_C2C_MASK (1 << 1)
+
+/* CLK_GATE_IP_ACP */
+#define CLK_SMMUG2D_MASK (1 << 7)
+#define CLK_SMMUSSS_MASK (1 << 6)
+#define CLK_SMMUMDMA_MASK (1 << 5)
+#define CLK_ID_REMAPPER_MASK (1 << 4)
+#define CLK_G2D_MASK (1 << 3)
+#define CLK_SSS_MASK (1 << 2)
+#define CLK_MDMA_MASK (1 << 1)
+#define CLK_SECJTAG_MASK (1 << 0)
+
+/* CLK_GATE_BUS_SYSLFT */
+#define CLK_EFCLK_MASK (1 << 16)
+
+/* CLK_GATE_IP_ISP0 */
+#define CLK_UART_ISP_MASK (1 << 31)
+#define CLK_WDT_ISP_MASK (1 << 30)
+#define CLK_PWM_ISP_MASK (1 << 28)
+#define CLK_MTCADC_ISP_MASK (1 << 27)
+#define CLK_I2C1_ISP_MASK (1 << 26)
+#define CLK_I2C0_ISP_MASK (1 << 25)
+#define CLK_MPWM_ISP_MASK (1 << 24)
+#define CLK_MCUCTL_ISP_MASK (1 << 23)
+#define CLK_INT_COMB_ISP_MASK (1 << 22)
+#define CLK_SMMU_MCUISP_MASK (1 << 13)
+#define CLK_SMMU_SCALERP_MASK (1 << 12)
+#define CLK_SMMU_SCALERC_MASK (1 << 11)
+#define CLK_SMMU_FD_MASK (1 << 10)
+#define CLK_SMMU_DRC_MASK (1 << 9)
+#define CLK_SMMU_ISP_MASK (1 << 8)
+#define CLK_GICISP_MASK (1 << 7)
+#define CLK_ARM9S_MASK (1 << 6)
+#define CLK_MCUISP_MASK (1 << 5)
+#define CLK_SCALERP_MASK (1 << 4)
+#define CLK_SCALERC_MASK (1 << 3)
+#define CLK_FD_MASK (1 << 2)
+#define CLK_DRC_MASK (1 << 1)
+#define CLK_ISP_MASK (1 << 0)
+
+/* CLK_GATE_IP_ISP1 */
+#define CLK_SPI1_ISP_MASK (1 << 13)
+#define CLK_SPI0_ISP_MASK (1 << 12)
+#define CLK_SMMU3DNR_MASK (1 << 7)
+#define CLK_SMMUDIS1_MASK (1 << 6)
+#define CLK_SMMUDIS0_MASK (1 << 5)
+#define CLK_SMMUODC_MASK (1 << 4)
+#define CLK_3DNR_MASK (1 << 2)
+#define CLK_DIS_MASK (1 << 1)
+#define CLK_ODC_MASK (1 << 0)
+
+/* CLK_GATE_IP_GSCL */
+#define CLK_SMMUFIMC_LITE2_MASK (1 << 20)
+#define CLK_SMMUFIMC_LITE1_MASK (1 << 12)
+#define CLK_SMMUFIMC_LITE0_MASK (1 << 11)
+#define CLK_SMMUGSCL3_MASK (1 << 10)
+#define CLK_SMMUGSCL2_MASK (1 << 9)
+#define CLK_SMMUGSCL1_MASK (1 << 8)
+#define CLK_SMMUGSCL0_MASK (1 << 7)
+#define CLK_GSCL_WRAP_B_MASK (1 << 6)
+#define CLK_GSCL_WRAP_A_MASK (1 << 5)
+#define CLK_CAMIF_TOP_MASK (1 << 4)
+#define CLK_GSCL3_MASK (1 << 3)
+#define CLK_GSCL2_MASK (1 << 2)
+#define CLK_GSCL1_MASK (1 << 1)
+#define CLK_GSCL0_MASK (1 << 0)
+
+/* CLK_GATE_IP_MFC */
+#define CLK_SMMUMFCR_MASK (1 << 2)
+#define CLK_SMMUMFCL_MASK (1 << 1)
+#define CLK_MFC_MASK (1 << 0)
+
+#define SCLK_MPWM_ISP_MASK (1 << 0)
+
+/* CLK_GATE_IP_DISP1 */
+#define CLK_SMMUTVX_MASK (1 << 9)
+#define CLK_ASYNCTVX_MASK (1 << 7)
+#define CLK_HDMI_MASK (1 << 6)
+#define CLK_MIXER_MASK (1 << 5)
+#define CLK_DSIM1_MASK (1 << 3)
+
+/* AUDIO CLK SEL */
+#define AUDIO0_SEL_EPLL (0x6 << 28)
+#define AUDIO0_RATIO 0x5
+#define PCM0_RATIO 0x3
+#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
+
+/* CLK_GATE_IP_GEN */
+#define CLK_SMMUMDMA1_MASK (1 << 9)
+#define CLK_SMMUJPEG_MASK (1 << 7)
+#define CLK_SMMUROTATOR_MASK (1 << 6)
+#define CLK_MDMA1_MASK (1 << 4)
+#define CLK_JPEG_MASK (1 << 2)
+#define CLK_ROTATOR_MASK (1 << 1)
+
+/* CLK_GATE_IP_FSYS */
+#define CLK_WDT_IOP_MASK (1 << 30)
+#define CLK_SMMUMCU_IOP_MASK (1 << 26)
+#define CLK_SATA_PHY_I2C_MASK (1 << 25)
+#define CLK_SATA_PHY_CTRL_MASK (1 << 24)
+#define CLK_MCUCTL_MASK (1 << 23)
+#define CLK_NFCON_MASK (1 << 22)
+#define CLK_SMMURTIC_MASK (1 << 11)
+#define CLK_RTIC_MASK (1 << 9)
+#define CLK_MIPI_HSI_MASK (1 << 8)
+#define CLK_USBOTG_MASK (1 << 7)
+#define CLK_SATA_MASK (1 << 6)
+#define CLK_PDMA1_MASK (1 << 2)
+#define CLK_PDMA0_MASK (1 << 1)
+#define CLK_MCU_IOP_MASK (1 << 0)
+
+/* CLK_GATE_IP_PERIC */
+#define CLK_HS_I2C3_MASK (1 << 31)
+#define CLK_HS_I2C2_MASK (1 << 30)
+#define CLK_HS_I2C1_MASK (1 << 29)
+#define CLK_HS_I2C0_MASK (1 << 28)
+#define CLK_AC97_MASK (1 << 27)
+#define CLK_SPDIF_MASK (1 << 26)
+#define CLK_PCM2_MASK (1 << 23)
+#define CLK_PCM1_MASK (1 << 22)
+#define CLK_I2S2_MASK (1 << 21)
+#define CLK_I2S1_MASK (1 << 20)
+#define CLK_SPI2_MASK (1 << 18)
+#define CLK_SPI0_MASK (1 << 16)
+#define CLK_I2CHDMI_MASK (1 << 14)
+#define CLK_I2C7_MASK (1 << 13)
+#define CLK_I2C6_MASK (1 << 12)
+#define CLK_I2C5_MASK (1 << 11)
+#define CLK_I2C4_MASK (1 << 10)
+#define CLK_I2C3_MASK (1 << 9)
+#define CLK_I2C2_MASK (1 << 8)
+#define CLK_I2C1_MASK (1 << 7)
+#define CLK_I2C0_MASK (1 << 6)
+
+/* CLK_GATE_IP_PERIS */
+#define CLK_RTC_MASK (1 << 20)
+#define CLK_TZPC9_MASK (1 << 15)
+#define CLK_TZPC8_MASK (1 << 14)
+#define CLK_TZPC7_MASK (1 << 13)
+#define CLK_TZPC6_MASK (1 << 12)
+#define CLK_TZPC5_MASK (1 << 11)
+#define CLK_TZPC4_MASK (1 << 10)
+#define CLK_TZPC3_MASK (1 << 9)
+#define CLK_TZPC2_MASK (1 << 8)
+#define CLK_TZPC1_MASK (1 << 7)
+#define CLK_TZPC0_MASK (1 << 6)
+#define CLK_CHIPID_MASK (1 << 0)
+
+/* CLK_GATE_BLOCK */
+#define CLK_ACP_MASK (1 << 7)
+
+/* CLK_GATE_IP_CDREX */
+#define CLK_TZASC_DRBXW_MASK (1 << 23)
+#define CLK_TZASC_DRBXR_MASK (1 << 22)
+#define CLK_TZASC_XLBXW_MASK (1 << 21)
+#define CLK_TZASC_XLBXR_MASK (1 << 20)
+#define CLK_TZASC_XR1BXW_MASK (1 << 19)
+#define CLK_TZASC_XR1BXR_MASK (1 << 18)
+#define CLK_DPHY1_MASK (1 << 5)
+#define CLK_DPHY0_MASK (1 << 4)
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+
+#define LPDDR3PHY_CTRL_PHY_RESET (1 << 0)
+#define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
+
+/* FIXME(dhendrix): misleading name. The reset value is 0x17021a40, bits 12:11
++ default to 0x3 which indicates LPDDR3. We want DDR3, so we use 0x1. */
+#define PHY_CON0_RESET_VAL 0x17020a40
+#define P0_CMD_EN (1 << 14)
+#define BYTE_RDLVL_EN (1 << 13)
+#define CTRL_SHGATE (1 << 8)
+
+#define PHY_CON1_RESET_VAL 0x09210100
+#define RDLVL_PASS_ADJ_VAL 0x6
+#define RDLVL_PASS_ADJ_OFFSET 16
+#define CTRL_GATEDURADJ_MASK (0xf << 20)
+#define READ_LEVELLING_DDR3 0x0100
+
+#define PHY_CON2_RESET_VAL 0x00010004
+#define INIT_DESKEW_EN (1 << 6)
+#define DLL_DESKEW_EN (1 << 12)
+#define RDLVL_GATE_EN (1 << 24)
+#define RDLVL_EN (1 << 25)
+#define RDLVL_INCR_ADJ (0x1 << 16)
+
+/* DREX_PAUSE */
+#define DREX_PAUSE_EN (1 << 0)
+
+#define BYPASS_EN (1 << 22)
+
+/********-----MEMMORY VAL----------***/
+#define PHY_CON0_VAL 0x17021A00
+
+#define PHY_CON12_RESET_VAL 0x10100070
+#define PHY_CON12_VAL 0x10107F50
+#define CTRL_START (1 << 6)
+#define CTRL_DLL_ON (1 << 5)
+#define CTRL_FORCE_MASK (0x7F << 8)
+#define CTRL_LOCK_COARSE_MASK (0x7F << 10)
+
+
+#define CTRL_OFFSETD_RESET_VAL 0x8
+#define CTRL_OFFSETD_VAL 0x7F
+
+#define CTRL_OFFSETR0 0x7F
+#define CTRL_OFFSETR1 0x7F
+#define CTRL_OFFSETR2 0x7F
+#define CTRL_OFFSETR3 0x7F
+#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
+ CTRL_OFFSETR1 << 8 | \
+ CTRL_OFFSETR2 << 16 | \
+ CTRL_OFFSETR3 << 24)
+#define PHY_CON4_RESET_VAL 0x08080808
+
+#define CTRL_OFFSETW0 0x7F
+#define CTRL_OFFSETW1 0x7F
+#define CTRL_OFFSETW2 0x7F
+#define CTRL_OFFSETW3 0x7F
+#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
+ CTRL_OFFSETW1 << 8 | \
+ CTRL_OFFSETW2 << 16 | \
+ CTRL_OFFSETW3 << 24)
+#define PHY_CON6_RESET_VAL 0x08080808
+
+#define PHY_CON14_RESET_VAL 0x001F0000
+#define CTRL_PULLD_DQS 0xF
+#define CTRL_PULLD_DQS_OFFSET 0
+
+/*ZQ Configurations */
+#define PHY_CON16_RESET_VAL 0x08000304
+
+#define ZQ_CLK_EN (1 << 27)
+#define ZQ_CLK_DIV_EN (1 << 18)
+#define ZQ_MANUAL_MODE_OFFSET 2
+#define ZQ_LONG_CALIBRATION 0x1
+#define ZQ_MANUAL_STR (1 << 1)
+#define ZQ_DONE (1 << 0)
+#define ZQ_MODE_DDS_OFFSET 24
+
+#define LONG_CALIBRATION (ZQ_LONG_CALIBRATION << ZQ_MANUAL_MODE_OFFSET)
+
+#define CTRL_RDLVL_GATE_ENABLE 1
+#define CTRL_RDLVL_GATE_DISABLE 0
+
+#define CTRL_RDLVL_DATA_ENABLE (1 << 1)
+/* Direct Command */
+#define DIRECT_CMD_NOP 0x07000000
+#define DIRECT_CMD_PALL 0x01000000
+#define DIRECT_CMD_ZQINIT 0x0a000000
+#define DIRECT_CMD_CHANNEL_SHIFT 28
+#define DIRECT_CMD_CHIP_SHIFT 20
+#define DIRECT_CMD_BANK_SHIFT 16
+#define DIRECT_CMD_REFA (5 << 24)
+#define DIRECT_CMD_MRS1 0x71C00
+#define DIRECT_CMD_MRS2 0x10BFC
+#define DIRECT_CMD_MRS3 0x0050C
+#define DIRECT_CMD_MRS4 0x00868
+#define DIRECT_CMD_MRS5 0x00C04
+
+/* Drive Strength */
+#define IMPEDANCE_48_OHM 4
+#define IMPEDANCE_40_OHM 5
+#define IMPEDANCE_34_OHM 6
+#define IMPEDANCE_30_OHM 7
+#define PHY_CON39_VAL_48_OHM 0x09240924
+#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
+#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
+#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
+
+
+#define CTRL_BSTLEN_OFFSET 8
+#define CTRL_RDLAT_OFFSET 0
+
+#define CMD_DEFAULT_LPDDR3 0xF
+#define CMD_DEFUALT_OFFSET 0
+#define T_WRDATA_EN 0x7
+#define T_WRDATA_EN_DDR3 0x8 /* FIXME(dhendrix): 6 for DDR3? see T_wrdata_en */
+#define T_WRDATA_EN_OFFSET 16
+#define T_WRDATA_EN_MASK 0x1f
+
+#define PHY_CON31_VAL 0x0C183060
+#define PHY_CON32_VAL 0x60C18306
+#define PHY_CON33_VAL 0x00000030
+
+#define PHY_CON31_RESET_VAL 0x0
+#define PHY_CON32_RESET_VAL 0x0
+#define PHY_CON33_RESET_VAL 0x0
+
+#define SL_DLL_DYN_CON_EN (1 << 1)
+#define FP_RESYNC (1 << 3)
+#define CTRL_START (1 << 6)
+
+#define DMC_AREF_EN (1 << 5)
+#define DMC_CONCONTROL_EMPTY (1 << 8)
+#define DFI_INIT_START (1 << 28)
+
+#define DMC_MEMCONTROL_VAL 0x00312700
+#define CLK_STOP_EN (1 << 0)
+#define DPWRDN_EN (1 << 1)
+#define DSREF_EN (1 << 5)
+
+/* AXI base address mask */
+#define DMC_CHIP_MASK_256MB 0x7f0
+#define DMC_CHIP_MASK_512MB 0x7e0
+#define DMC_CHIP_MASK_1GB 0x7c0
+#define DMC_CHIP_MASK_2GB 0x780
+#define DMC_CHIP_MASK_4GB 0x700
+
+#define MEMCONFIG_VAL 0x1323
+#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
+#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
+
+#define DFI_INIT_COMPLETE (1 << 3)
+
+#define BRBRSVCONTROL_VAL 0x00000033
+#define BRBRSVCONFIG_VAL 0x88778877
+
+/* Clock Gating Control (CGCONTROL) register */
+#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
+#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
+#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
+#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
+#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
+ BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
+
+/* DMC PHY Control0 register */
+#define PHY_CONTROL0_RESET_VAL 0x0
+#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
+#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
+#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
+#define CTRL_ATGATE (1 << 6)
+#define FP_RSYNC (1 << 3) /* Force DLL resynchronization */
+
+/* Driver strength for CK, CKE, CS & CA */
+#define IMP_OUTPUT_DRV_40_OHM 0x5
+#define IMP_OUTPUT_DRV_30_OHM 0x7
+#define DA_3_DS_OFFSET 25
+#define DA_2_DS_OFFSET 22
+#define DA_1_DS_OFFSET 19
+#define DA_0_DS_OFFSET 16
+#define CA_CK_DRVR_DS_OFFSET 9
+#define CA_CKE_DRVR_DS_OFFSET 6
+#define CA_CS_DRVR_DS_OFFSET 3
+#define CA_ADR_DRVR_DS_OFFSET 0
+
+#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+
+struct mem_timings;
+
+/* Errors that we can encounter in low-level setup */
+enum {
+ SETUP_ERR_OK,
+ SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
+ SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
+};
+
+/* Functions common between LPDDR2 and DDR3 */
+
+/* CPU info initialization code */
+void cpu_info_init(void);
+
+void mem_ctrl_init(void);
+/*
+ * Memory variant specific initialization code
+ *
+ * @param mem Memory timings for this memory type.
+ * @param mem_iv_size Memory interleaving size is a configurable parameter
+ * which the DMC uses to decide how to split a memory
+ * chunk into smaller chunks to support concurrent
+ * accesses; may vary across boards.
+ * @param mem_reset Reset memory during initialization.
+ * @return 0 if ok, SETUP_ERR_... if there is a problem
+ */
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset);
+
+/* Memory variant specific initialization code for LPDDR3 */
+int lpddr3_mem_ctrl_init(int reset);
+
+/*
+ * Configure ZQ I/O interface
+ *
+ * @param mem Memory timings for this memory type.
+ * @param phy0_ctrl Pointer to struct containing PHY0 control reg
+ * @param phy1_ctrl Pointer to struct containing PHY1 control reg
+ * @return 0 if ok, -1 on error
+ */
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_control *phy0_ctrl,
+ struct exynos5_phy_control *phy1_ctrl);
+
+/*
+ * Send NOP and MRS/EMRS Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param dmc Pointer to struct of DMC registers
+ */
+void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
+
+/*
+ * Send PALL Direct commands
+ *
+ * @param mem Memory timings for this memory type.
+ * @param dmc Pointer to struct of DMC registers
+ */
+void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
+
+/*
+ * Configure the memconfig and membaseconfig registers
+ *
+ * @param mem Memory timings for this memory type.
+ * @param exynos5_dmc Pointer to struct of DMC registers
+ */
+void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
+
+/*
+ * Reset the DLL. This function is common between DDR3 and LPDDR2.
+ * However, the reset value is different. So we are passing a flag
+ * ddr_mode to distinguish between LPDDR2 and DDR3.
+ *
+ * @param exynos5_dmc Pointer to struct of DMC registers
+ * @param ddr_mode Type of DDR memory
+ */
+void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/spi.h b/src/soc/samsung/exynos5420/include/soc/spi.h
new file mode 100644
index 0000000000..78cca6f416
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/spi.h
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_SPI_H
+#define CPU_SAMSUNG_EXYNOS5420_SPI_H
+
+/* This driver serves as a CBFS media source. */
+#include <cbfs.h>
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+ unsigned int ch_cfg; /* 0x00 */
+ unsigned char reserved0[4];
+ unsigned int mode_cfg; /* 0x08 */
+ unsigned int cs_reg; /* 0x0c */
+ unsigned char reserved1[4];
+ unsigned int spi_sts; /* 0x14 */
+ unsigned int tx_data; /* 0x18 */
+ unsigned int rx_data; /* 0x1c */
+ unsigned int pkt_cnt; /* 0x20 */
+ unsigned char reserved2[4];
+ unsigned int swap_cfg; /* 0x28 */
+ unsigned int fb_clk; /* 0x2c */
+ unsigned char padding[0xffd0];
+};
+check_member(exynos_spi, fb_clk, 0x2c);
+
+#define EXYNOS_SPI_MAX_FREQ 50000000
+
+#define SPI_TIMEOUT_MS 10
+
+#define SF_READ_DATA_CMD 0x3
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN (1 << 6)
+#define SPI_CH_RST (1 << 5)
+#define SPI_SLAVE_MODE (1 << 4)
+#define SPI_CH_CPOL_L (1 << 3)
+#define SPI_CH_CPHA_B (1 << 2)
+#define SPI_RX_CH_ON (1 << 1)
+#define SPI_TX_CH_ON (1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_BUS_WIDTH_BYTE (0x0 << 17)
+#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
+#define SPI_MODE_BUS_WIDTH_MASK (0x3 << 17)
+#define SPI_MODE_CH_WIDTH_BYTE (0x0 << 29)
+#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
+#define SPI_MODE_CH_WIDTH_MASK (0x3 << 29)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT (1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE (1 << 25)
+#define SPI_FIFO_LVL_MASK 0x1ff
+#define SPI_TX_LVL_OFFSET 6
+#define SPI_RX_LVL_OFFSET 15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS (0 << 0)
+#define SPI_FB_DELAY_90 (1 << 0)
+#define SPI_FB_DELAY_180 (2 << 0)
+#define SPI_FB_DELAY_270 (3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN (1 << 16)
+
+/* Swap config */
+#define SPI_TX_SWAP_EN (1 << 0)
+#define SPI_TX_BYTE_SWAP (1 << 2)
+#define SPI_TX_HWORD_SWAP (1 << 3)
+#define SPI_TX_BYTE_SWAP (1 << 2)
+#define SPI_RX_SWAP_EN (1 << 4)
+#define SPI_RX_BYTE_SWAP (1 << 6)
+#define SPI_RX_HWORD_SWAP (1 << 7)
+
+/* Serve as CBFS media source */
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/sysreg.h b/src/soc/samsung/exynos5420/include/soc/sysreg.h
new file mode 100644
index 0000000000..d2f1bdefea
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/sysreg.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Register map for Exynos5 sysreg */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_SYSREG_H
+#define CPU_SAMSUNG_EXYNOS5420_SYSREG_H
+
+#include <soc/cpu.h>
+
+/* sysreg map */
+struct exynos5_sysreg {
+ /* Add registers as and when required */
+ unsigned char res1[0x214];
+ unsigned int disp1blk_cfg;
+ unsigned char res2[0x18];
+ unsigned int usb20_phy_cfg;
+};
+check_member(exynos5_sysreg, usb20_phy_cfg, 0x230);
+
+static struct exynos5_sysreg * const exynos_sysreg =
+ (void *)EXYNOS5_SYSREG_BASE;
+
+#define FIMDBYPASS_DISP1 (1 << 15)
+#define USB20_PHY_CFG_EN (1 << 0)
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/tmu.h b/src/soc/samsung/exynos5420/include/soc/tmu.h
new file mode 100644
index 0000000000..f71c8993de
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/tmu.h
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* EXYNOS - Thermal Management Unit */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_TMU_H
+#define CPU_SAMSUNG_EXYNOS5420_TMU_H
+
+struct tmu_reg {
+ unsigned triminfo;
+ unsigned rsvd1;
+ unsigned rsvd2;
+ unsigned rsvd3;
+ unsigned rsvd4;
+ unsigned triminfo_control;
+ unsigned rsvd5;
+ unsigned rsvd6;
+ unsigned tmu_control;
+ unsigned rsvd7;
+ unsigned tmu_status;
+ unsigned sampling_internal;
+ unsigned counter_value0;
+ unsigned counter_value1;
+ unsigned rsvd8;
+ unsigned rsvd9;
+ unsigned current_temp;
+ unsigned rsvd10;
+ unsigned rsvd11;
+ unsigned rsvd12;
+ unsigned threshold_temp_rise;
+ unsigned threshold_temp_fall;
+ unsigned rsvd13;
+ unsigned rsvd14;
+ unsigned past_temp3_0;
+ unsigned past_temp7_4;
+ unsigned past_temp11_8;
+ unsigned past_temp15_12;
+ unsigned inten;
+ unsigned intstat;
+ unsigned intclear;
+ unsigned rsvd15;
+ unsigned emul_con;
+};
+check_member(tmu_reg, emul_con, 0x80);
+
+enum tmu_status_t {
+ TMU_STATUS_INIT = 0,
+ TMU_STATUS_NORMAL,
+ TMU_STATUS_WARNING,
+ TMU_STATUS_TRIPPED,
+};
+
+/* Temperature threshold values for various thermal events */
+struct temperature_params {
+ /* minimum value in temperature code range */
+ unsigned int min_val;
+ /* maximum value in temperature code range */
+ unsigned int max_val;
+ /* temperature threshold to start warning */
+ unsigned int start_warning;
+ /* temperature threshold CPU tripping */
+ unsigned int start_tripping;
+ /* temperature threshold for HW tripping */
+ unsigned int hardware_tripping;
+};
+
+/* Pre-defined values and thresholds for calibration of current temperature */
+struct tmu_data {
+ /* pre-defined temperature thresholds */
+ struct temperature_params ts;
+ /* pre-defined efuse range minimum value */
+ unsigned int efuse_min_value;
+ /* pre-defined efuse value for temperature calibration */
+ unsigned int efuse_value;
+ /* pre-defined efuse range maximum value */
+ unsigned int efuse_max_value;
+ /* current temperature sensing slope */
+ unsigned int slope;
+};
+
+/* TMU device specific details and status */
+struct tmu_info {
+ /* base Address for the TMU */
+ unsigned tmu_base;
+ /* mux Address for the TMU */
+ int tmu_mux;
+ /* pre-defined values for calibration and thresholds */
+ struct tmu_data data;
+ /* value required for triminfo_25 calibration */
+ unsigned int te1;
+ /* value required for triminfo_85 calibration */
+ unsigned int te2;
+ /* TMU DC value for threshold calculation */
+ int dc_value;
+ /* enum value indicating status of the TMU */
+ int tmu_state;
+};
+
+extern struct tmu_info *tmu_info;
+
+/*
+ * Monitors status of the TMU device and exynos temperature
+ *
+ * @info pointer to TMU info struct
+ * @temp pointer to the current temperature value
+ * @return enum tmu_status_t value, code indicating event to execute
+ * and -1 on error
+ */
+enum tmu_status_t tmu_monitor(struct tmu_info *info, int *temp);
+
+/*
+ * Initialize TMU device
+ *
+ * @info pointer to TMU info struct
+ * @return int value, 0 for success
+ */
+int tmu_init(struct tmu_info *info);
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_TMU_H */
diff --git a/src/soc/samsung/exynos5420/include/soc/trustzone.h b/src/soc/samsung/exynos5420/include/soc/trustzone.h
new file mode 100644
index 0000000000..209cd9f354
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/trustzone.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H
+#define CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H
+
+#include <stdint.h>
+
+/* Distance between each Trust Zone PC register set */
+#define TZPC_BASE_OFFSET 0x10000
+/* TZPC : Register Offsets */
+#define TZPC0_BASE 0x10100000
+#define TZPC1_BASE 0x10110000
+#define TZPC2_BASE 0x10120000
+#define TZPC3_BASE 0x10130000
+#define TZPC4_BASE 0x10140000
+#define TZPC5_BASE 0x10150000
+#define TZPC6_BASE 0x10160000
+#define TZPC7_BASE 0x10170000
+#define TZPC8_BASE 0x10180000
+#define TZPC9_BASE 0x10190000
+#define TZPC10_BASE 0x100E0000
+#define TZPC11_BASE 0x100F0000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+
+struct exynos_tzpc {
+ u32 r0size;
+ u8 res1[0x7FC];
+ u32 decprot0stat;
+ u32 decprot0set;
+ u32 decprot0clr;
+ u32 decprot1stat;
+ u32 decprot1set;
+ u32 decprot1clr;
+ u32 decprot2stat;
+ u32 decprot2set;
+ u32 decprot2clr;
+ u32 decprot3stat;
+ u32 decprot3set;
+ u32 decprot3clr;
+ u8 res2[0x7B0];
+ u32 periphid0;
+ u32 periphid1;
+ u32 periphid2;
+ u32 periphid3;
+ u32 pcellid0;
+ u32 pcellid1;
+ u32 pcellid2;
+ u32 pcellid3;
+};
+check_member(exynos_tzpc, pcellid3, 0xffc);
+
+void trustzone_init(void);
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_TRUSTZONE_H */
diff --git a/src/soc/samsung/exynos5420/include/soc/uart.h b/src/soc/samsung/exynos5420/include/soc/uart.h
new file mode 100644
index 0000000000..ed78f60cc3
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/uart.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ * Copyright (C) 2009 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_UART_H
+#define CPU_SAMSUNG_EXYNOS5420_UART_H
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ unsigned char res3[0xffd0];
+};
+check_member(s5p_uart, ubrdiv, 0x28);
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/usb.h b/src/soc/samsung/exynos5420/include/soc/usb.h
new file mode 100644
index 0000000000..12571057b6
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/usb.h
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_USB_H
+#define CPU_SAMSUNG_EXYNOS5420_USB_H
+
+#include <soc/cpu.h>
+
+#define CLK_24MHZ 5
+
+#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
+#define HOST_CTRL0_COMMONON_N (1 << 9)
+#define HOST_CTRL0_SIDDQ (1 << 6)
+#define HOST_CTRL0_FORCESLEEP (1 << 5)
+#define HOST_CTRL0_FORCESUSPEND (1 << 4)
+#define HOST_CTRL0_WORDINTERFACE (1 << 3)
+#define HOST_CTRL0_UTMISWRST (1 << 2)
+#define HOST_CTRL0_LINKSWRST (1 << 1)
+#define HOST_CTRL0_PHYSWRST (1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK (7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN (1 << 29)
+#define EHCICTRL_ENAINCR4 (1 << 28)
+#define EHCICTRL_ENAINCR8 (1 << 27)
+#define EHCICTRL_ENAINCR16 (1 << 26)
+
+/* Register map for PHY control */
+struct exynos5_usb_host_phy {
+ uint32_t usbphyctrl0;
+ uint32_t usbphytune0;
+ uint8_t reserved1[8];
+ uint32_t hsicphyctrl1;
+ uint32_t hsicphytune1;
+ uint8_t reserved2[8];
+ uint32_t hsicphyctrl2;
+ uint32_t hsicphytune2;
+ uint8_t reserved3[8];
+ uint32_t ehcictrl;
+ uint32_t ohcictrl;
+ uint32_t usbotgsys;
+ uint8_t reserved4[4];
+ uint32_t usbotgtune;
+};
+check_member(exynos5_usb_host_phy, usbotgtune, 0x40);
+
+static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
+ (void *)EXYNOS5_USB_HOST_PHY_BASE;
+
+struct exynos5_usb_drd_phy {
+ uint8_t reserved1[4];
+ uint32_t linksystem;
+ uint32_t utmi;
+ uint32_t pipe;
+ uint32_t clkrst;
+ uint32_t reg0;
+ uint32_t reg1;
+ uint32_t param0;
+ uint32_t param1;
+ uint32_t term;
+ uint32_t test;
+ uint32_t adp;
+ uint32_t utmiclksel;
+ uint32_t resume;
+ uint8_t reserved2[8];
+ uint32_t linkhcbelt;
+ uint32_t linkport;
+};
+check_member(exynos5_usb_drd_phy, linkport, 0x44);
+
+static struct exynos5_usb_drd_phy * const exynos_usb_drd0_phy =
+ (void *)EXYNOS5420_USB_DRD0_PHY_BASE;
+static struct exynos5_usb_drd_phy * const exynos_usb_drd1_phy =
+ (void *)EXYNOS5420_USB_DRD1_PHY_BASE;
+
+struct exynos5_usb_drd_dwc3 {
+ uint32_t sbuscfg0;
+ uint32_t sbuscfg1;
+ uint32_t txthrcfg;
+ uint32_t rxthrcfg;
+ uint32_t ctl;
+ uint32_t evten;
+ uint32_t sts;
+ uint8_t reserved0[4];
+ uint32_t snpsid;
+ uint32_t gpio;
+ uint32_t uid;
+ uint32_t uctl;
+ uint64_t buserraddr;
+ uint64_t prtbimap;
+ uint8_t reserved1[32];
+ uint32_t dbgfifospace;
+ uint32_t dbgltssm;
+ uint32_t dbglnmcc;
+ uint32_t dbgbmu;
+ uint32_t dbglspmux;
+ uint32_t dbglsp;
+ uint32_t dbgepinfo0;
+ uint32_t dbgepinfo1;
+ uint64_t prtbimap_hs;
+ uint64_t prtbimap_fs;
+ uint8_t reserved2[112];
+ uint32_t usb2phycfg;
+ uint8_t reserved3[60];
+ uint32_t usb2i2cctl;
+ uint8_t reserved4[60];
+ uint32_t usb2phyacc;
+ uint8_t reserved5[60];
+ uint32_t usb3pipectl;
+ uint8_t reserved6[60];
+};
+check_member(exynos5_usb_drd_dwc3, usb3pipectl, 0x1c0);
+
+static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd0_dwc3 =
+ (void *)EXYNOS5420_USB_DRD0_DWC3_BASE;
+static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd1_dwc3 =
+ (void *)EXYNOS5420_USB_DRD1_DWC3_BASE;
+
+/* Leave hsic_gpio at 0 to not enable HSIC. */
+void setup_usb_host_phy(int hsic_gpio);
+
+void setup_usb_drd0_phy(void);
+void setup_usb_drd1_phy(void);
+
+/* Call reset_ before setup_, ensure at least 100ms pass in between. */
+void reset_usb_drd0_dwc3(void);
+void reset_usb_drd1_dwc3(void);
+void setup_usb_drd0_dwc3(void);
+void setup_usb_drd1_dwc3(void);
+
+#endif
diff --git a/src/soc/samsung/exynos5420/include/soc/wakeup.h b/src/soc/samsung/exynos5420/include/soc/wakeup.h
new file mode 100644
index 0000000000..27ce8e2f2d
--- /dev/null
+++ b/src/soc/samsung/exynos5420/include/soc/wakeup.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5420_WAKEUP_H
+#define CPU_SAMSUNG_EXYNOS5420_WAKEUP_H
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+enum {
+ // A normal boot (not suspend/resume)
+ IS_NOT_WAKEUP,
+ // A wake up event that can be resumed any time
+ WAKEUP_DIRECT,
+ // A wake up event that must be resumed only after
+ // clock and memory controllers are re-initialized
+ WAKEUP_NEED_CLOCK_RESET,
+};
+
+int wakeup_need_reset(void);
+int get_wakeup_state(void);
+void wakeup(void);
+void wakeup_enable_uart(void);
+
+#endif /* CPU_SAMSUNG_EXYNOS5420_WAKEUP_H */