diff options
| author | John Su <john_su@compal.corp-partner.google.com> | 2022-06-08 16:35:18 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-10 22:05:38 +0000 |
| commit | f32a533931845f7974b25dda7191eac40ef831e5 (patch) | |
| tree | e097356260384b2989154b6602282ab578691b12 /src/soc/rockchip | |
| parent | 52e5538d4aa8078ad646ea46aaa1af916b6b8137 (diff) | |
mb/google/brya/variants/felwinter: Enable TBT PCIe Root Port 0
The TBT device can't be recognized after we re-plug it at DB type-c
port. Intel found that tbt_pcie_rp0 has mapping error after each
re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this
problem and take this as short term solution. Intel will implement
re-mapping mechanism in ACPI for long term solution.
BUG=b:230141802
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I61429033dfe64d67916167bb901bdd8246db953e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions