summaryrefslogtreecommitdiff
path: root/src/soc/rockchip
diff options
context:
space:
mode:
authorWerner Zeh <werner.zeh@siemens.com>2022-12-22 11:09:34 +0100
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2023-01-10 00:30:59 +0000
commitce6cdb360810938ab5800cb2d9f4f3c6e4d9fad8 (patch)
tree91afbcb8c131fd374f08935e1da430e285effe1f /src/soc/rockchip
parent921bb34c919a617706f269b89333b5dede59880f (diff)
mb/siemens/mc_ehl1: Limit SATA speed to Gen 2
Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/rockchip')
0 files changed, 0 insertions, 0 deletions