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authorMoritz Fischer <moritzf@google.com>2021-02-17 14:25:25 -0800
committerron minnich <rminnich@gmail.com>2021-02-18 21:23:49 +0000
commita76f659840d41a8840be936df2567649f510ef93 (patch)
tree5d575bea0a4441048c3027a0acb749f7273b3ca7 /src/soc/rockchip
parentc4ca8c355678dc329ec713a3079e6e56956c9bd9 (diff)
soc/rockchip/rk3399/sdram: Order and group tsel variables
Order and group tsel variables in a meaningful way. No functional changes. Signed-off-by: Moritz Fischer <moritzf@google.com> Change-Id: I417e0fbc129c2d9ad1b345bcff2e25ca6eca83bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/50866 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/rockchip')
-rw-r--r--src/soc/rockchip/rk3399/sdram.c30
1 files changed, 18 insertions, 12 deletions
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index aa12e81e84..b0545213f6 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -182,34 +182,40 @@ static void set_ds_odt(u32 channel, const struct rk3399_sdram_params *params)
if (params->dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_wr_select_p = PHY_DRV_ODT_40;
- ca_tsel_wr_select_p = PHY_DRV_ODT_40;
+ tsel_wr_select_n = PHY_DRV_ODT_40;
+
tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
+ tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_n = PHY_DRV_ODT_40;
+ ca_tsel_wr_select_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_n = PHY_DRV_ODT_40;
- tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (params->dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240;
+ tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
+
tsel_wr_select_p = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_p = PHY_DRV_ODT_48;
+ tsel_wr_select_n = PHY_DRV_ODT_34_3;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
- tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
- tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ ca_tsel_wr_select_p = PHY_DRV_ODT_48;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
- tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
} else {
tsel_rd_select_p = PHY_DRV_ODT_240;
+ tsel_rd_select_n = PHY_DRV_ODT_240;
+
tsel_wr_select_p = PHY_DRV_ODT_34_3;
- ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
+ tsel_wr_select_n = PHY_DRV_ODT_34_3;
+
tsel_idle_select_p = PHY_DRV_ODT_240;
+ tsel_idle_select_n = PHY_DRV_ODT_240;
- tsel_rd_select_n = PHY_DRV_ODT_240;
- tsel_wr_select_n = PHY_DRV_ODT_34_3;
+ ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
- tsel_idle_select_n = PHY_DRV_ODT_240;
}
if (params->odt == 1)