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authorDerek Basehore <dbasehore@chromium.org>2015-03-03 12:30:43 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:18:12 +0200
commit5c8aacfa3dd51ecd598f4062c3e5c4f4891cc78e (patch)
tree6270473414e3249cca451453e6e5682b9aab72e2 /src/soc/rockchip
parent9eb6f6161a82c144915ad37f93cba03597b4c905 (diff)
rockchip: configure lpddr odt properly
The wrong offsets were being used for the GRF_SOC_CON2 register. This also configures odt based on the value of odt in the sdram_params for lpddr systems. BUG=chrome-os-partner:37346 TEST=boot veyron_speedy and veyron_jerry BRANCH=None Change-Id: I13ec3d0df162fe73fabf8af40dd5472e15d6f6af Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 403ab13de17290dc3766bd6f1a03b6effbe58b41 Original-Change-Id: Ic0c18cc7ccf861ef8749e6c950fab9a2802e5f26 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255584 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip')
-rw-r--r--src/soc/rockchip/rk3288/sdram.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index 3d547cde25..44f9172bee 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -456,11 +456,11 @@ static struct rk3288_msch_regs * const rk3288_msch[2] = {
| ((1 << (3 + (ch))) << 16))
/* GRF_SOC_CON2 */
-#define PUBL_LPDDR3_EN(ch, n) RK_CLRSETBITS(1 << (10 + (3 * (ch))), \
+#define PCTL_LPDDR3_ODT_EN(ch, n) RK_CLRSETBITS(1 << (10 + (3 * (ch))), \
(n) << (10 + (3 * (ch))))
-#define PCTL_LPDDR3_ODT_EN(ch, n) RK_CLRSETBITS(1 << (9 + (3 * (ch))), \
+#define PCTL_BST_DISABLE(ch, n) RK_CLRSETBITS(1 << (9 + (3 * (ch))), \
(n) << (9 + (3 * (ch))))
-#define PCTL_BST_DISABLE(ch, n) RK_CLRSETBITS(1 << (8 + (3 * (ch))), \
+#define PUBL_LPDDR3_EN(ch, n) RK_CLRSETBITS(1 << (8 + (3 * (ch))), \
(n) << (8 + (3 * (ch))))
/* mr1 for ddr3 */
@@ -616,7 +616,7 @@ static void pctl_cfg(u32 channel,
writel(PUBL_LPDDR3_EN(channel, 1)
| PCTL_BST_DISABLE(channel, 1)
- | PCTL_LPDDR3_ODT_EN(channel, 1),
+ | PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt),
&rk3288_grf->soc_con2);
break;