diff options
author | Lin Huang <hl@rock-chips.com> | 2016-03-23 19:24:53 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-09 08:46:42 +0200 |
commit | bf48fbbcc116b79fa5bfe05db83c354ee87e3843 (patch) | |
tree | ec259ca22f496383fad4ab8a18a265c09c64b838 /src/soc/rockchip/rk3399/saradc.c | |
parent | 08d177b091be4758c7b541a5f9550b849e6dd092 (diff) |
rockchip: rk3399: support saradc
This patch add functions to configure saradc clk and get
saradc's raw value for each channel.
Currently add saradc to ramstage.
Please refer to TRM V0.3 Part 2 Chapter 18 for this IP.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=on kevin board, get the raw value 61 for channel 0,
measure the ADC_IN0 as 0.109V,
61.0/1024 = 0.05957 0.109V/1.8V = 0.06056
Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a
Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/334177
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14720
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/saradc.c')
-rw-r--r-- | src/soc/rockchip/rk3399/saradc.c | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c new file mode 100644 index 0000000000..d70c9667fc --- /dev/null +++ b/src/soc/rockchip/rk3399/saradc.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/clock.h> +#include <soc/saradc.h> +#include <stdint.h> +#include <stdlib.h> +#include <timer.h> + +struct rk3399_saradc_regs { + u32 data; + u32 stas; + u32 ctrl; + u32 dly_pu_soc; +}; +check_member(rk3399_saradc_regs, dly_pu_soc, 0xc); + +struct rk3399_saradc_regs *rk3399_saradc = (void *)SARADC_BASE; + +/* SARADC_STAS: conversion done */ +#define ADC_STOP 0 + +/* SARADC_CTRL */ +#define INT_EN (1 << 5) +#define ADC_PWR_CTRL (1 << 3) +#define ADC_CHN_SEL_MASK 7 +#define ADC_CHN_SEL_SHIFT 0 + +/* SARADC_DATA, 10[0:9] bits */ +#define DATA_MASK 0x3FF + +/* The max clk is 13 MHz, we also recommended that + * the sample rate(=clk/13) should be > 500KHz. + * So choose 8MHz, that 8MHz/13 = 615.38KHz > 500KHz. + */ +#define SARADC_HZ (8*MHz) + +/* TRM(V0.3 Part 1 Page 366) said there is a delay between + * power up and start command, default value is 2 src clk. + * Let delay 2 src clk here, in ns(udelay). + */ +#define SARADC_DELAY_PU (1 * 1000 * 1000 * 1000 / SARADC_HZ * 2) + +#define SARADC_MAX_CHANNEL 6 + +u32 get_saradc_value(u32 chn) +{ + u32 adc_value; + struct stopwatch sw; + + assert(chn < SARADC_MAX_CHANNEL); + rkclk_configure_saradc(SARADC_HZ); + + /* power down adc converter */ + clrbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + + /* select channel */ + clrsetbits_le32(&rk3399_saradc->ctrl, + ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, + chn << ADC_CHN_SEL_SHIFT); + + /* power up */ + setbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + + udelay(SARADC_DELAY_PU); + + stopwatch_init_msecs_expire(&sw, 10); + do { + if (read32(&rk3399_saradc->stas) == ADC_STOP) { + adc_value = read32(&rk3399_saradc->data) & DATA_MASK; + return adc_value; + } + } while (!stopwatch_expired(&sw)); + + return -1; +} |