diff options
| author | William wu <wulf@rock-chips.com> | 2016-10-01 20:58:21 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-10-08 16:40:09 +0200 |
| commit | 801a8ef2c3c209e0f44978b677f7b03cde209f21 (patch) | |
| tree | 4345dae0b9c3d4860f6c262a8cbe76072156db55 /src/soc/rockchip/rk3399/include | |
| parent | aa9df0f0dec62794dbea1d97852fc0d32a81ca14 (diff) | |
rockchip/rk3399: Add Type-C PHY init
Though we don't use Type-C PHY to support USB3 in firmware,
we still need to initialize the Type-C PHY, and make sure
the power state of pipe is always fixed to U2/P2. After
this, we can force USB3 controller to work in USB2 only
mode.
BRANCH=none
BUG=chrome-os-partner:56425
TEST=Go to recovery mode, plug a Type-C USB drive containing
chrome OS image into both ports in all orientations, check if
system can boot from USB.
Change-Id: I95bb96ff27d4fecafb7b2b9e9dc2839b5c132654
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ec98507845276119d8a9d5626934dedcb35f2dd
Original-Change-Id: Ie3654cd1c1cb76b62aa9b247879b60cbecee0155
Original-Signed-off-by: William wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/391412
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16910
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/usb.h | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/usb.h b/src/soc/rockchip/rk3399/include/soc/usb.h index 46d3752328..c2fa1a2af4 100644 --- a/src/soc/rockchip/rk3399/include/soc/usb.h +++ b/src/soc/rockchip/rk3399/include/soc/usb.h @@ -111,12 +111,41 @@ static struct rockchip_usb_dwc3 * const rockchip_usb_otg0_dwc3 = static struct rockchip_usb_dwc3 * const rockchip_usb_otg1_dwc3 = (void *)USB_OTG1_DWC3_BASE; -/* TODO: define struct overlay if we ever need more registers from this */ -#define TCPHY_ISOLATION_CTRL_OFFSET 0x3207c #define TCPHY_ISOLATION_CTRL_EN (1 << 15) #define TCPHY_ISOLATION_CTRL_CMN_EN (1 << 14) #define TCPHY_ISOLATION_CTRL_MODE_SEL (1 << 12) #define TCPHY_ISOLATION_CTRL_LN_EN(ln) (1 << (ln)) +#define TCPHY_CMN_HSCLK_PLL_CONFIG 0x30 +#define TCPHY_CMN_HSCLK_PLL_MASK 0x33 + +struct rk3399_tcphy { + uint8_t _res0[0x780 - 0x0]; + uint32_t cmn_diag_hsclk_sel; + uint8_t _res1[0x10000 - 0x784]; + struct { + uint8_t _res2[0x3c8 - 0x0]; + uint32_t xcvr_diag_lane_fcm_en_mgn; + uint8_t _res3[0x408 - 0x3cc]; + uint32_t tx_psc_a2; + uint8_t _res4[0x488 - 0x40c]; + uint32_t tx_rcvdet_en_tmr; + uint32_t tx_rcvdet_st_tmr; + uint8_t _res5[0x784 - 0x490]; + uint32_t tx_diag_tx_drv; + uint8_t _res6[0x800 - 0x788]; + } lane[4]; + uint8_t _res7[0x32000 - 0x12000]; + uint32_t pma_cmn_ctrl1; + uint8_t _res8[0x3207c - 0x32004]; + uint32_t isolation_ctrl; +}; +check_member(rk3399_tcphy, lane[2].tx_diag_tx_drv, 0x11784); +check_member(rk3399_tcphy, isolation_ctrl, 0x3207c); + +static struct rk3399_tcphy * const rockchip_usb_otg0_phy = + (void *)USB_OTG0_TCPHY_BASE; +static struct rk3399_tcphy * const rockchip_usb_otg1_phy = + (void *)USB_OTG1_TCPHY_BASE; /* Call reset_ before setup_ */ void reset_usb_otg0(void); |