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authorLin Huang <hl@rock-chips.com>2016-10-20 14:22:11 -0700
committerPatrick Georgi <pgeorgi@google.com>2016-11-02 17:31:21 +0100
commit152e675fd952bbb0e7d786fbaa7711b8d0d454f2 (patch)
treebd5b17aaac9549b9d5b4e001ad8feadeb18f23e0 /src/soc/rockchip/rk3399/include
parent13acd35d6fa2623dce970acae9296b80a75ed2a3 (diff)
rockchip/rk3399: display: Do not allocate framebuffer in coreboot
framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
-rw-r--r--src/soc/rockchip/rk3399/include/soc/display.h3
-rw-r--r--src/soc/rockchip/rk3399/include/soc/memlayout.ld1
2 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h
index 7ccde5611a..c10f1b9f04 100644
--- a/src/soc/rockchip/rk3399/include/soc/display.h
+++ b/src/soc/rockchip/rk3399/include/soc/display.h
@@ -18,8 +18,7 @@
#define REF_CLK_24M (0x1 << 0)
-void rk_display_init(device_t dev, uintptr_t lcdbase,
- unsigned long fb_size);
+void rk_display_init(device_t dev);
void mainboard_power_on_backlight(void);
#endif
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index a441281de9..f440dfb391 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -22,7 +22,6 @@ SECTIONS
POSTRAM_CBFS_CACHE(0x00100000, 1M)
RAMSTAGE(0x00300000, 256K)
DMA_COHERENT(0x10000000, 2M)
- FRAMEBUFFER(0x10200000, 16M)
/* 8K of special SRAM in PMU power domain. */
SYMBOL(pmu_sram, 0xFF3B0000)