diff options
| author | Lin Huang <hl@rock-chips.com> | 2017-02-22 18:22:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-19 18:43:19 +0200 |
| commit | aaf6322a1172d4833c6f190616db6f27dcd77377 (patch) | |
| tree | 080342fd44b8348313c61c956fb0ec00e4ef7e78 /src/soc/rockchip/rk3399/clock.c | |
| parent | 9a848dde8b34a854af716670f5c993c49c1ab22e (diff) | |
rockchip/rk3399: fix DRAM gate training issue
The differential signal of DQS needs to keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it. But if it has PHY side ODT
connected at this time, it will change the DQS
signal level. So it needs to disable PHY side ODT
when doing gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f
Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448278
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
0 files changed, 0 insertions, 0 deletions