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authorJulius Werner <jwerner@chromium.org>2019-12-02 22:03:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-04 14:11:17 +0000
commit55009af42c39f413c49503670ce9bc2858974962 (patch)
tree099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/rockchip/rk3399/clock.c
parent1c371572188a90ea16275460dd4ab6bf9966350b (diff)
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
-rw-r--r--src/soc/rockchip/rk3399/clock.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 5252232f39..f9c49c33d7 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -374,9 +374,9 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
write32(&cru_ptr->dpll_con[3],
RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT,
PLL_FRAC_MODE << PLL_DSMPD_SHIFT));
- clrsetbits_le32(&cru_ptr->dpll_con[2],
- PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT,
- 0 << PLL_FRACDIV_SHIFT);
+ clrsetbits32(&cru_ptr->dpll_con[2],
+ PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT,
+ 0 << PLL_FRACDIV_SHIFT);
/*
* Configure SSC divval.