rockchip: rk3399: support basic clock driver

This patch initialize the PLL clocks and add function to
configure cpu freq. Right now, we set the little cpu freq to 600MHz.

In coreboot, we currently care about these four PLLs,
o. APLL for cpu clk, where A stands for AXI,
o. CPLL and GPLL are the generic PLL mainly for peripheral clk,
o. PPLL is only PMU clk.

For the peripheral clocks, there are thress clocks named as,
 aclk_perihp,
 aclk_perilp0,
 hclk_perilp1,
where the 'h' and 'l' letters refer to High and Low speed.
As the diagram below, the aclk_perihp always be the parent of
more higher speed peripheral devices like pcie, and
hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto.
These three clocks can choose parent from GPLL or CPLL freely,
in this patch, they are all sourced from GPLL.

GPLL(594M)/CPLL(384M)                      APLL(600M for little core)
   |                                           |
   `-- aclk_perihp                             `-- clk_core(600M == APLL)
   |       |                                           |
   |       `-- periph_aclk(148.5M)                     `-- atclk_core(300M)
   |       `-- periph_hclk(148.5M)                     `-- aclkm_core(300M)
   |       `-- periph_pclk(37.125M)                    `-- pclk_dbg_core(100M)
   |
   `-- hclk_perilp1
   |       |
   |       `-- periph_hclk(99M)            PPLL(594M)
   |       `-- periph_pclk(49.5M)              |
   |                                           `-- pmu_pclk(99M)
   `-- aclk_perilp0
           |
           `-- periph_aclk(99M)
           `-- periph_hclk(99M)
           `-- periph_pclk(49.5M)

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c
Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332386
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 3 insertions, 5 deletions

diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c
index ae41a083f4..d87f967d5f 100644
--- a/src/soc/rockchip/rk3399/bootblock.c
+++ b/src/soc/rockchip/rk3399/bootblock.c
@@ -11,15 +11,13 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
  */
 
-#include <arch/io.h>
-#include <arch/mmu.h>
 #include <bootblock_common.h>
-#include <console/console.h>
-#include <symbols.h>
+#include <soc/clock.h>
 
 void bootblock_soc_init(void)
 {
+	rkclk_init();
+	rkclk_configure_cpu(APLL_L_600_MHZ);
 }