diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-06-15 17:43:40 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-23 17:13:40 +0200 |
| commit | 50df52244ebeb019c9e4f78a1197d7200f759b51 (patch) | |
| tree | d2a30d9c5530513e277d294b3fde15eeac42fe49 /src/soc/rockchip/rk3399/Makefile.inc | |
| parent | 9e6b0ee2c4dc9130091eff45989b4585c4a2bf83 (diff) | |
rockchip/rk3399: Clean up voltage rail settings
The CENTER LOGIC should always be 0.9V and can not be adjusted,
so use duty_ns = 2860 to correct CENTER LOGIC to 0.9V. And now
DDR seems to run stable at 800MHz on the gru board.
BRANCH=none
BUG=chrome-os-partner:54144, chrome-os-partner:53208
TEST=run "stressapptest -M 1024 -s 1000" and pass
Change-Id: Ia900e248c10ddd0ab630446a324cc0446c0fa49b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: f4fb1cefb59ac4099cef8b32a68ed9222e708478
Original-Change-Id: I2238da6c17908d09bc284b321d796901317ed9ef
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/352772
Reviewed-on: https://review.coreboot.org/15297
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/Makefile.inc')
| -rw-r--r-- | src/soc/rockchip/rk3399/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 990edcba2c..28c633835a 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -49,6 +49,7 @@ romstage-y += romstage.c romstage-y += tsadc.c romstage-y += usb.c romstage-y += gpio.c +romstage-y += saradc.c romstage-y += ../common/gpio.c ################################################################################ |