rockchip: refactor gpio driver

The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP,
moving the gpio code of rk3288 to common then can be reused on rk3399.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=build and boot into chromeos on veyron_jerry

Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779
Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339846
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 0 insertions, 66 deletions

diff --git a/src/soc/rockchip/rk3288/include/soc/gpio.h b/src/soc/rockchip/rk3288/include/soc/gpio.h
deleted file mode 100644
index 05b30b9627..0000000000
--- a/src/soc/rockchip/rk3288/include/soc/gpio.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_ROCKCHIP_RK3288_GPIO_H__
-#define __SOC_ROCKCHIP_RK3288_GPIO_H__
-
-#include <types.h>
-
-#define GPIO(p, b, i) ((gpio_t){.port = p, .bank = GPIO_##b, .idx = i})
-
-struct rk3288_gpio_regs {
-	u32 swporta_dr;
-	u32 swporta_ddr;
-	u32 reserved0[(0x30 - 0x08) / 4];
-	u32 inten;
-	u32 intmask;
-	u32 inttype_level;
-	u32 int_polarity;
-	u32 int_status;
-	u32 int_rawstatus;
-	u32 debounce;
-	u32 porta_eoi;
-	u32 ext_porta;
-	u32 reserved1[(0x60 - 0x54) / 4];
-	u32 ls_sync;
-};
-check_member(rk3288_gpio_regs, ls_sync, 0x60);
-
-typedef union {
-	u32 raw;
-	struct {
-		u16 port;
-		union {
-			struct {
-				u16 num:5;
-				u16 :11;
-			};
-			struct {
-				u16 idx:3;
-				u16 bank:2;
-				u16 :11;
-			};
-		};
-	};
-} gpio_t;
-
-enum {
-	GPIO_A = 0,
-	GPIO_B,
-	GPIO_C,
-	GPIO_D,
-};
-
-#endif	/* __SOC_ROCKCHIP_RK3288_GPIO_H__ */