diff options
| author | David Hendricks <dhendrix@chromium.org> | 2015-09-18 12:46:01 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-25 07:31:34 +0100 |
| commit | c8c099f1ea142250efa392234c6ba98058eba9b5 (patch) | |
| tree | c2592f826cfca5d8e0eeac302937f6d463301da5 /src/soc/rockchip/rk3288/include | |
| parent | 67a71ea230e1678f3e281ba7431cdbab7ec9e8b1 (diff) | |
rockchip/rk3288: Add 600MHz as an option for RK3288 APLL
BUG=chrome-os-partner:41201
BRANCH=firmware-veyron
TEST=tested with subsequent patch on mickey
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I7081d92be128f522e1a33eee6f3de9dfbbf042ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a390c927ad8ed035520c8a813db808715dc5e527
Original-Change-Id: I3ce0f7b2772c8c652b7f461749d01cc7b669b6cf
Original-Reviewed-on: https://chromium-review.googlesource.com/300616
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12134
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/include')
| -rw-r--r-- | src/soc/rockchip/rk3288/include/soc/clock.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 3fccecb8f2..995f4e51c2 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -31,6 +31,7 @@ enum apll_frequencies { APLL_1800_MHZ, APLL_1392_MHZ, + APLL_600_MHZ, }; /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */ |