From c8c099f1ea142250efa392234c6ba98058eba9b5 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 18 Sep 2015 12:46:01 -0700 Subject: rockchip/rk3288: Add 600MHz as an option for RK3288 APLL BUG=chrome-os-partner:41201 BRANCH=firmware-veyron TEST=tested with subsequent patch on mickey Signed-off-by: David Hendricks Change-Id: I7081d92be128f522e1a33eee6f3de9dfbbf042ea Signed-off-by: Patrick Georgi Original-Commit-Id: a390c927ad8ed035520c8a813db808715dc5e527 Original-Change-Id: I3ce0f7b2772c8c652b7f461749d01cc7b669b6cf Original-Reviewed-on: https://chromium-review.googlesource.com/300616 Original-Commit-Ready: David Hendricks Original-Tested-by: David Hendricks Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/12134 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/rockchip/rk3288/include/soc/clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/rockchip/rk3288/include') diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 3fccecb8f2..995f4e51c2 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -31,6 +31,7 @@ enum apll_frequencies { APLL_1800_MHZ, APLL_1392_MHZ, + APLL_600_MHZ, }; /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */ -- cgit v1.2.3