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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-09-26 18:21:48 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2018-10-01 04:15:30 +0000 |
| commit | 339ae162b6a666d558c49a6794966f5e339e76e7 (patch) | |
| tree | 877e378f8b210f685f1fdd6d89cd3e01f5b9b2ad /src/soc/rockchip/rk3288/clock.c | |
| parent | 1e67f0773bff13b6ced9e9cf101917538f49c48b (diff) | |
soc/intel/fsp_broadwell_de: Fix IA32_MC0_* names
Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and
IA32_MC0_CTL is at 0x400.
So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at
0x400 by IA32_MC0_CTL.
Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
0 files changed, 0 insertions, 0 deletions