rockchip/common: Loosen I2C frequency target requirements

I've recently added an assertion to ensure that the effective I2C
frequency on Rockchip SoCs is not too far off the 400KHz target due to
divisor rounding errors. A 10KHz margin worked fine for RK3399, but it
turns out that RK3288 actually only ever hit 387KHz since its I2C clocks
are based off the already pretty low 75MHz PCLKs. While we could
probably change the PCLKs to make this closer, that seems like a too
intrusive change for something that has already worked just fine for
years, so just loosen the restriction a little more instead.

BRANCH=None
BUG=chromium:675043
TEST=None

Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421095
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/18007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c
index a00d538ba2..032efda9b2 100644
--- a/src/soc/rockchip/common/i2c.c
+++ b/src/soc/rockchip/common/i2c.c
@@ -286,6 +286,6 @@ void i2c_init(unsigned int bus, unsigned int hz)
 	i2c_clk = i2c_src_clk / (8 * (divl + 1 + divh + 1));
 	printk(BIOS_DEBUG, "I2C bus %u: %uHz (divh = %u, divl = %u)\n",
 	       bus, i2c_clk, divh, divl);
-	assert((divh < 65536) && (divl < 65536) && hz - i2c_clk < 10*KHz);
+	assert((divh < 65536) && (divl < 65536) && hz - i2c_clk < 15*KHz);
 	write32(&regs->i2c_clkdiv, (divh << 16) | (divl << 0));
 }