diff options
| author | Shunqian Zheng <zhengsq@rock-chips.com> | 2016-05-17 14:00:04 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-12 00:28:33 +0200 |
| commit | 74bb41275326cd34046454ab5a06bd7a17d5f887 (patch) | |
| tree | 58757d2d15ffd8bbc2853ac577f1d94d44e7ee37 /src/soc/rockchip/common | |
| parent | 5d49b4a4bcbc878256dac40ef834e07ea7101673 (diff) | |
rockchip/rk3399: Fix pinctrl pull bias settings
The pull bias settings for GPIO0_A, GPIO0_B, GPIO2_C and GPIO2_D
are different from the other GPIO banks.
This patch adds a callback function to get the GPIO pull value
of each SoC(rk3288 and rk3399) so we can still use the common
GPIO driver.
BRANCH=none
BUG=chrome-os-partner:53251
TEST=Jerry and Gru still boot
Change-Id: I2a00b7ffd2699190582f5f50a1e21b61c500bf4f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 46d5fa7297693216a2da9bcf15ccce4af796e80e
Original-Change-Id: If53f47181bdc235a1ccfefeeb2a77e0eb0e3b1ca
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358110
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15587
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip/common')
| -rw-r--r-- | src/soc/rockchip/common/gpio.c | 11 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/gpio.h | 10 |
2 files changed, 13 insertions, 8 deletions
diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 6f30229817..6ea38d4d5f 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -21,21 +21,16 @@ #include <soc/soc.h> #include <stdlib.h> -enum { - PULLNONE = 0, - PULLUP, - PULLDOWN -}; - static void __gpio_input(gpio_t gpio, u32 pull) { + u32 pull_val = gpio_get_pull_val(gpio, pull); clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); if (is_pmu_gpio(gpio)) clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), - pull << (gpio.idx * 2)); + pull_val << (gpio.idx * 2)); else write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), - pull << (gpio.idx * 2))); + pull_val << (gpio.idx * 2))); } void gpio_input(gpio_t gpio) diff --git a/src/soc/rockchip/common/include/soc/gpio.h b/src/soc/rockchip/common/include/soc/gpio.h index 55eb41d980..2c72435065 100644 --- a/src/soc/rockchip/common/include/soc/gpio.h +++ b/src/soc/rockchip/common/include/soc/gpio.h @@ -72,4 +72,14 @@ int is_pmu_gpio(gpio_t gpio); /* Return the io addr of gpio register */ void *gpio_grf_reg(gpio_t gpio); + +enum { + PULLNONE = 0, + PULLUP, + PULLDOWN +}; + +/* The gpio pull bias setting may be different between SoCs */ +u32 gpio_get_pull_val(gpio_t gpio, u32 pull); + #endif |