diff options
| author | Taniya Das <tdas@codeaurora.org> | 2021-06-23 09:08:57 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2021-09-16 17:14:20 +0000 |
| commit | e3cf008d88447b8a9ee3c08f755dcee4ada80a77 (patch) | |
| tree | 0539449cd07387d20c9740e168faa1fe80472cf6 /src/soc/qualcomm | |
| parent | 75a29bc92c137642d81dbd8d799c4b2ad7e07c08 (diff) | |
soc/qualcomm: clock: Clean up clock driver
Updated return type as CB_SUCCESS and aligned indentation.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/soc/qualcomm')
| -rw-r--r-- | src/soc/qualcomm/sc7180/clock.c | 6 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7280/clock.c | 3 |
2 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index aa289c4c79..4497b9c663 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -164,12 +164,12 @@ static enum cb_err pll_init_and_set(struct sc7180_apss_clock *apss, u32 l_val) pll_cfg.l_val = l_val; ret = clock_configure_enable_gpll(&pll_cfg, false, 0); - if (ret < 0) + if (ret != CB_SUCCESS) return CB_ERR; pll_cfg.reg_mode = &apss->pll.mode; ret = agera_pll_enable(&pll_cfg); - if (ret < 0) + if (ret != CB_SUCCESS) return CB_ERR; gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK; @@ -224,7 +224,7 @@ int mdss_clock_enable(enum mdss_clock clk_type) if (clk_type >= MDSS_CLK_COUNT) return CB_ERR; - /* Enable clock*/ + /* Enable clock */ return clock_enable(mdss_cbcr[clk_type]); } diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index 871fb9bbd8..07a575b952 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -255,7 +255,6 @@ void clock_configure_qspi(uint32_t hz) clock_enable(&gcc->qspi_core_cbcr); } - void clock_enable_qup(int qup) { struct qupv3_clock *qup_clk; @@ -412,7 +411,7 @@ enum cb_err mdss_clock_enable(enum clk_mdss clk_type) if (clk_type >= MDSS_CLK_COUNT) return CB_ERR; - /* Enable clock*/ + /* Enable clock */ return clock_enable(mdss_cbcr[clk_type]); } |