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authorSubrata Banik <subratabanik@google.com>2023-04-06 19:53:49 +0530
committerSubrata Banik <subratabanik@google.com>2023-04-11 11:39:14 +0000
commitcc4ca5ec94a112b6d585dcbd14c71f182131fed8 (patch)
tree03b799afcb1fa96a5ac7904092ff0c84c33b4d50 /src/soc/qualcomm
parent589f6b9c049434967ffe668d084ca1bd1a3946fa (diff)
mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB
This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/soc/qualcomm')
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