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authorShelley Chen <shchen@google.com>2021-10-07 23:09:36 -0700
committerShelley Chen <shchen@google.com>2021-10-15 15:38:34 +0000
commit9573c0ed3adbca869cf1b88312a10cc72b756547 (patch)
tree97c2d144f428195d2e3368eb9b56bc055fcd5ab5 /src/soc/qualcomm
parentad6f87d61202984e7604a35b6ce5babee614e676 (diff)
soc/qualcomm/sc7280: Enable compression of SHRM
The SHRM region needs to be 4 byte aligned, which make enabling compression slightly more complicated. We need to map it to cached memory before loading it and flushing to memory (in aligned chunks) then remapping the address space back to device memory before beginning execution of the SHRM region. Also, did some cleanup in this file based on comments in CB:49392. BUG=b:182963902 BRANCH=None TEST=Make sure we can still boot to kernel on herobrine Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm')
-rw-r--r--src/soc/qualcomm/sc7280/Makefile.inc2
-rw-r--r--src/soc/qualcomm/sc7280/shrm_load_reset.c18
2 files changed, 15 insertions, 5 deletions
diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc
index 364c987dc6..442b2a3858 100644
--- a/src/soc/qualcomm/sc7280/Makefile.inc
+++ b/src/soc/qualcomm/sc7280/Makefile.inc
@@ -107,7 +107,7 @@ SHRM_FILE := $(SC7280_BLOB)/shrm/shrm.elf
SHRM_CBFS := $(CONFIG_CBFS_PREFIX)/shrm
$(SHRM_CBFS)-file := $(SHRM_FILE)
$(SHRM_CBFS)-type := payload
-$(SHRM_CBFS)-compression := none
+$(SHRM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG)
cbfs-files-y += $(SHRM_CBFS)
endif
diff --git a/src/soc/qualcomm/sc7280/shrm_load_reset.c b/src/soc/qualcomm/sc7280/shrm_load_reset.c
index 78830a2df1..e25d95230e 100644
--- a/src/soc/qualcomm/sc7280/shrm_load_reset.c
+++ b/src/soc/qualcomm/sc7280/shrm_load_reset.c
@@ -1,22 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/cache.h>
+#include <arch/mmu.h>
#include <cbfs.h>
#include <console/console.h>
#include <soc/mmu.h>
+#include <soc/mmu_common.h>
#include <soc/shrm.h>
#include <soc/clock.h>
+#include <soc/symbols_common.h>
void shrm_fw_load_reset(void)
{
- bool shrm_fw_entry;
struct prog shrm_fw_prog =
PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/shrm");
- shrm_fw_entry = selfload(&shrm_fw_prog);
- if (!shrm_fw_entry)
+ /* map to cached region to force address to be 4 byte aligned */
+ mmu_config_range((void *)_shrm, REGION_SIZE(shrm), CACHED_RAM);
+
+ if (!selfload(&shrm_fw_prog))
die("SOC image: SHRM load failed");
+ /* flush cached region */
+ dcache_clean_by_mva(_shrm, REGION_SIZE(shrm));
+ /* remap back to device memory */
+ mmu_config_range((void *)_shrm, REGION_SIZE(shrm), DEV_MEM);
+
clock_reset_shrm();
- printk(BIOS_DEBUG, "\nSOC:SHRM brought out of reset.\n");
+ printk(BIOS_DEBUG, "SOC:SHRM brought out of reset.\n");
}