diff options
| author | Taniya Das <quic_tdas@quicinc.com> | 2022-07-04 21:02:31 +0530 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-14 21:15:24 +0000 |
| commit | 6b81bcdb6b4aef797e3ac1eaf1acfd6906510df3 (patch) | |
| tree | a1170e63ac333ba2f7db8b40853b7d645e5f6dc5 /src/soc/qualcomm/sc7280/socinfo.c | |
| parent | f48f1fdc84098ab3055d88f79fae7d3f88f13428 (diff) | |
soc/qualcomm/sc7280: Add SocInfo support in coreboot
Add support for SocInfo in coreboot. The API socinfo_modem_supported is
added to help to differentiate between LTE and WiFi SKUs.
BUG=b:232302324
TEST=Validate boards are detected correctly on LTE and Wifi SKUs
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: I61047ad49772c3796ba403cafde311ad184a4093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/soc/qualcomm/sc7280/socinfo.c')
| -rw-r--r-- | src/soc/qualcomm/sc7280/socinfo.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7280/socinfo.c b/src/soc/qualcomm/sc7280/socinfo.c new file mode 100644 index 0000000000..6e66abea67 --- /dev/null +++ b/src/soc/qualcomm/sc7280/socinfo.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <commonlib/helpers.h> +#include <device/mmio.h> +#include <types.h> +#include <soc/socinfo.h> +#include <soc/addressmap.h> + +#define JTAG_OFFSET 0xB1014 + +static struct chipinfo chipinfolut[] = { + { CHIPINFO_ID_SM_KODIAK, CHIPINFO_PARTNUM_SM_KODIAK, CHIPINFO_MODEM_SUPPORTED}, + { CHIPINFO_ID_SC_KODIAK_CHROME, CHIPINFO_PARTNUM_SC_KODIAK_CHROME, + CHIPINFO_MODEM_SUPPORTED }, + { CHIPINFO_ID_SC_KODIAK_WINDOWS, CHIPINFO_PARTNUM_SC_KODIAK_WINDOWS, + CHIPINFO_MODEM_SUPPORTED}, + { CHIPINFO_ID_QCM_KODIAK, CHIPINFO_PARTNUM_QCM_KODIAK, CHIPINFO_MODEM_SUPPORTED }, + { CHIPINFO_ID_QCS_KODIAK, CHIPINFO_PARTNUM_QCS_KODIAK, CHIPINFO_MODEM_UNKNOWN }, + { CHIPINFO_ID_SMP_KODIAK, CHIPINFO_PARTNUM_SMP_KODIAK, CHIPINFO_MODEM_UNKNOWN }, + { CHIPINFO_ID_SM_KODIAK_LTE_ONLY, CHIPINFO_PARTNUM_SM_KODIAK_LTE_ONLY, + CHIPINFO_MODEM_SUPPORTED }, + { CHIPINFO_ID_SCP_KODIAK, CHIPINFO_PARTNUM_SCP_KODIAK, CHIPINFO_MODEM_UNKNOWN }, + { CHIPINFO_ID_SC_8CGEN3, CHIPINFO_PARTNUM_SC_8CGEN3, CHIPINFO_MODEM_SUPPORTED }, + { CHIPINFO_ID_SCP_8CGEN3, CHIPINFO_PARTNUM_SCP_8CGEN3, CHIPINFO_MODEM_UNKNOWN }, + { CHIPINFO_ID_KODIAK_SCP_7CGEN3, CHIPINFO_PARTNUM_KODIAK_SCP_7CGEN3, + CHIPINFO_MODEM_UNKNOWN }, + { CHIPINFO_ID_QCS_KODIAK_LITE, CHIPINFO_PARTNUM_QCS_KODIAK_LITE, + CHIPINFO_MODEM_UNKNOWN }, + { CHIPINFO_ID_QCM_KODIAK_LITE, CHIPINFO_PARTNUM_QCM_KODIAK_LITE, + CHIPINFO_MODEM_UNKNOWN }, +}; + +bool socinfo_modem_supported(void) +{ + uint32_t jtagid; + int i; + + jtagid = read32((void *)(TLMM_TILE_BASE + JTAG_OFFSET)) & DEVICE_ID; + + for (i = 0; i < ARRAY_SIZE(chipinfolut); i++) + if (chipinfolut[i].jtagid == jtagid) + return chipinfolut[i].modem; + + return false; +} |