diff options
| author | Prasad Malisetty <quic_pmaliset@quicinc.com> | 2022-07-25 13:35:05 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-08-01 18:04:54 +0000 |
| commit | 78298f5c8f46c6615655b2711a76b61bf8218378 (patch) | |
| tree | 24ffa5ce577bcf30f712c49ed8cc1dc305be8af2 /src/soc/qualcomm/sc7280/soc.c | |
| parent | a47a4906353f8d534b0ce1d573082008decb8697 (diff) | |
soc/qualcomm/sc7280: Enable PCIe driver
Enable PCIe functionality on sc7280 and supply all the needed data
for PCIe generic platform driver.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7280/soc.c')
| -rw-r--r-- | src/soc/qualcomm/sc7280/soc.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index c0c6a87934..a6851dfcd7 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -6,6 +6,14 @@ #include <soc/symbols_common.h> #include <soc/aop_common.h> #include <soc/cpucp.h> +#include <soc/pcie.h> + +static struct device_operations pci_domain_ops = { + .read_resources = &qcom_pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .enable = &qcom_setup_pcie_host, +}; static void soc_read_resources(struct device *dev) { @@ -36,7 +44,11 @@ static struct device_operations soc_ops = { static void enable_soc_dev(struct device *dev) { - dev->ops = &soc_ops; + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + dev->ops = &soc_ops; } struct chip_operations soc_qualcomm_sc7280_ops = { |