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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-22 17:38:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-23 18:03:15 +0000 |
| commit | f66e781336e992f0791480bd710ef32b71d4ad52 (patch) | |
| tree | fdff43d6c94abc5026e7ac5cd87ab13d21c9b15d /src/soc/qualcomm/sc7180/qupv3_spi.c | |
| parent | a754aa6d29f2078cffac6559a9efca6f9ce862ac (diff) | |
soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fch
Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/qupv3_spi.c')
0 files changed, 0 insertions, 0 deletions