summaryrefslogtreecommitdiff
path: root/src/soc/qualcomm/sc7180/qclib.c
diff options
context:
space:
mode:
authorMartin Roth <martinroth@chromium.org>2020-12-02 16:37:58 -0700
committerFelix Held <felix-coreboot@felixheld.de>2020-12-03 23:44:28 +0000
commit6a62cc85e61da5282611c2bee5ac3a54580f0113 (patch)
treefda57c0c88be089d805c9978b034b2865c6dcd90 /src/soc/qualcomm/sc7180/qclib.c
parent361a5c095262adc139f0d7504fb25e1215eebc8f (diff)
mb/google/zork: Set S0IX_SLP_L high in S0, low in S3
This is used as a signal to show the system state. It hadn't been used up to this point as we're not currently using S0i3, but the fingerprint sensor will use it to go into a low power mode, so set it appropriately on Trembyle. Dalboz devices don't use the FPMCU, but set there as well so that the state matches. BUG=b:174695987 TEST=Verify GPIO state in S0 and S3 with the EC BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Vincent Palatin <vpalatin@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/qclib.c')
0 files changed, 0 insertions, 0 deletions