diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-02-20 01:06:10 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-07 13:26:49 +0000 |
| commit | a5bdf8e8df7c2afe0264c58537569d6142d145cd (patch) | |
| tree | aa933a0d633e7a9b7b43fd2ca71381b98034e6e9 /src/soc/qualcomm/sc7180/include | |
| parent | cb6a35edd591fffa2e21a001a466d2fbd4baf04a (diff) | |
soc/intel/xeon_sp: Add memory type check utils
FSP memory type representations change across Xeon-SP SoCs.
This patch adds type check utils to abstract the differences.
TEST=intel/archercity CRB
Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/qualcomm/sc7180/include')
0 files changed, 0 insertions, 0 deletions