diff options
| author | Taniya Das <tdas@codeaurora.org> | 2019-12-19 16:41:02 +0530 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-02-07 23:12:00 +0000 |
| commit | 91dc1e74a52ec33dc7f5c33dca73f02c5fe54cf0 (patch) | |
| tree | d12a349c19549d7f1443fee76ba938a0dcccb416 /src/soc/qualcomm/sc7180/include | |
| parent | bcd62f5737f5022b1bbe0041d4222575851b3cb9 (diff) | |
sc7180: clock: Fix QUP DFSR configuration for perf levels
Update the QUP DFSR cmd to clear the SW control and also update the perf
registers when M is set. While at it also update the d_2 values.
Tested: validated DFSR clock configuration and M/N/D values.
Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/include')
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/clock.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 2e44b60623..383e6d7be2 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -187,6 +187,7 @@ enum clk_ctl_bcr { enum clk_ctl_dfsr { CLK_CTL_CMD_DFSR_BMSK = 0x1, CLK_CTL_CMD_DFSR_SHFT = 0, + CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, }; enum clk_qup { |