diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-06-11 11:59:07 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-13 06:49:23 +0000 |
| commit | 46514c2b877c29c2d7c2061a9785736e270c0c62 (patch) | |
| tree | 2f78550192bce548139ef49fdac6623dad578703 /src/soc/qualcomm/sc7180/include | |
| parent | 00148bba7146318e2e815d8c13e33278f63814c9 (diff) | |
treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/include')
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/memlayout.ld | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld deleted file mode 100644 index 2a0cd8a417..0000000000 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memlayout.h> -#include <arch/header.ld> - -/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ -#define SSRAM_START(addr) SYMBOL(ssram, addr) -#define SSRAM_END(addr) SYMBOL(essram, addr) - -/* BOOT_IMEM : 0x14800000 - 0x14980000 */ -#define BSRAM_START(addr) SYMBOL(bsram, addr) -#define BSRAM_END(addr) SYMBOL(ebsram, addr) - -/* AOP : 0x0B000000 - 0x0B100000 */ -#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) -#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) - -SECTIONS -{ - AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) - AOPSRAM_END(0x0B100000) - - SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - REGION(qcsdi, 0x14699000, 52K, 4K) - SSRAM_END(0x146AE000) - - BSRAM_START(0x14800000) - REGION(pbl_timestamps, 0x14800000, 84K, 4K) - BOOTBLOCK(0x14815000, 40K) - PRERAM_CBFS_CACHE(0x1481F000, 70K) - PRERAM_CBMEM_CONSOLE(0x14830800, 32K) - TIMESTAMP(0x14838800, 1K) - TTB(0x14839000, 56K) - STACK(0x14847000, 16K) - VBOOT2_WORK(0x1484B000, 12K) - DMA_COHERENT(0x1484E000, 8K) - REGION(ddr_training, 0x14850000, 8K, 4K) - REGION(qclib_serial_log, 0x14852000, 4K, 4K) - REGION(ddr_information, 0x14853000, 1K, 1K) - FMAP_CACHE(0x14853400, 2K) - REGION(dcb, 0x14870000, 16K, 4K) - REGION(pmic, 0x14874000, 44K, 4K) - REGION(limits_cfg, 0x1487F000, 4K, 4K) - REGION(qclib, 0x14880000, 512K, 4K) - BSRAM_END(0x14900000) - - DRAM_START(0x80000000) - /* Various hardware/software subsystems make use of this area */ - REGION(dram_aop, 0x80800000, 0x040000, 0x1000) - REGION(dram_soc, 0x80900000, 0x200000, 0x1000) - BL31(0x80B00000, 1M) - POSTRAM_CBFS_CACHE(0x9F800000, 16M) - RAMSTAGE(0xA0800000, 16M) -} |