diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-23 18:54:48 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-03 11:19:24 +0000 |
| commit | d05f57cfcbf069e9635c671c1ae53fcfced0c3b7 (patch) | |
| tree | 6198d7d347e1dd17e28e808c336063bab9750ace /src/soc/qualcomm/qcs405 | |
| parent | 2f389f151a0db244def706bc90fd17fe091d8537 (diff) | |
arch/arm64: Pass cbmem_top to ramstage via calling argument
This solution is very generic and can in principle be implemented on
all arch/soc. Currently the old infrastructure to pass on information
from romstage to ramstage is left in place and will be removed in a
follow-up commit.
Nvidia Tegra will be handled in a separate patch because it has a
custom ramstage entry.
Instead trying to figure out which files can be removed from stages
and which cbmem_top implementations need with preprocessor, rename all
cbmem_top implementation to cbmem_top_romstage.
Mechanisms set in place to pass on information from rom- to ram-stage
will be replaced in a followup commit.
Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/qcs405')
| -rw-r--r-- | src/soc/qualcomm/qcs405/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index f21ea542a9..0766d2f181 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -39,7 +39,6 @@ romstage-y += blsp.c ramstage-y += soc.c ramstage-y += timer.c ramstage-y += spi.c -ramstage-y += cbmem.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-y += i2c.c |